Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells
First Claim
1. A method of programming a row in an array of memory cells in a non-volatile memory device, the method comprising:
- programming the memory cells in the row;
verifying the programming of the memory cells by determining if each of the memory cells in each of a plurality of subsets of the memory cells in the row are properly programmed;
determining if less than a predetermined number of memory cells are not properly programmed in each of the subsets; and
in response to determining that less than a predetermined number of memory cells are not properly programmed in all of the subsets, providing a pseudo pass signal.
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Accused Products
Abstract
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry.
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Citations
49 Claims
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1. A method of programming a row in an array of memory cells in a non-volatile memory device, the method comprising:
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programming the memory cells in the row; verifying the programming of the memory cells by determining if each of the memory cells in each of a plurality of subsets of the memory cells in the row are properly programmed; determining if less than a predetermined number of memory cells are not properly programmed in each of the subsets; and in response to determining that less than a predetermined number of memory cells are not properly programmed in all of the subsets, providing a pseudo pass signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. In a non-volatile memory device having an array of memory cells arranged in rows and columns, a method of programming a row of non-volatile memory cells in the array, comprising:
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programming the memory cells in the row; verifying the programming of the memory cells by determining if the memory cells in each of a plurality of subsets of the memory cells in the row are properly programmed; determining if more than a predetermined number of memory cells are not properly programmed in any of the subsets; and in response to determining that more than a predetermined number of memory cells are not properly programmed in any of the subsets, repeating the programming and verifying of the memory cells in the row. - View Dependent Claims (8, 9, 10, 11, 12)
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13. In a processor-based system having a processor coupled to a non-volatile memory device having an array of memory cells arranged in rows and columns, the processor-based system further having error checking and correcting circuitry structured to check and correct sets of data read from the non-volatile memory device, a method of programming a row of memory cells in the array, comprising:
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programming the memory cells in the row; determining if the memory cells in each of a plurality of subsets of the memory cells in the row are properly programmed, each of the subsets of the memory cells storing respective ones of the subsets of data read from the non-volatile memory device; determining if more than a predetermined number of memory cells in any of the subsets are not properly programmed; and in response to determining that more than a predetermined number of memory cells in any of the subsets are not properly programmed, repeating the programming of the memory cells in the row. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. In a processor-based system having a processor coupled to a non-volatile memory device having an array of memory cells arranged in rows and columns, the processor-based system further having error checking and correcting circuitry structured to check and correct sets of data read from the non-volatile memory device, a method of programming a row of memory cells in the array, comprising:
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programming the memory cells in the row; determining if each of the memory cells in each of a plurality of subsets of the memory cells in the row are properly programmed, each of the subsets of the memory cells storing respective subsets of data read from the non-volatile memory device; determining if less than a predetermined number of memory cells are not properly programmed in each of the subsets; and in response to determining that less than a predetermined number of memory cells are not properly programmed in all of the subsets, providing a pseudo pass signal. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A non-volatile memory device, comprising:
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an array of non-volatile memory cells arranged in rows and columns; and a control logic unit coupled to the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address, the operations including programming memory cells in each row of the array and verifying the programming of the memory cells by determining if each of the memory cells in each of a plurality of subsets of the memory cells in the row are properly programmed; and a pseudo pass circuit coupled to the array and the control logic unit, the pseudo pass circuit being structured to determine if less than a predetermined number of memory cells are not properly programmed in all of the subsets, and in response thereto, to provide a pseudo pass signal. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 43)
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38. A processor-based system, comprising:
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a processor operable to process data and to provide memory commands and addresses; an input device coupled to the processor; an output device coupled to the processor; and a non-volatile memory device, comprising; an array of non-volatile memory cells arranged in rows and columns; and a control logic unit coupled to the array of non-volatile memory cells, the control logic being operable to carry out operations in the array corresponding to a memory command at a location in the array corresponding to a memory address, the operations including programming memory cells in each row of the array and verifying the programming of the memory cells by determining if each of the memory cells in each of a plurality of subsets of the memory cells in the row are properly programmed; and a pseudo pass circuit coupled to the array and the control logic unit, the pseudo pass circuit being structured to determine if less than a predetermined number of memory cells are not properly programmed in all of the subsets, and in response thereto, to provide a pseudo pass signal. - View Dependent Claims (39, 40, 41, 42, 44, 45, 46, 47, 48, 49)
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Specification