Semiconductor Nonvolatile Memory

• US 20080043537A1
• Filed: 05/14/2007
• Published: 02/21/2008
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Murata, Nobukazu, Tanikawa, Hiroyuki, Harada, Teruhiro
• Granted Patent: US 7,551,488 B2
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 2229/723 Redundancy information stored in a part of the memory core to be repaired
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.

Claims

1. A semiconductor nonvolatile memory comprising:

a memory array in which a plurality of first nonvolatile memory cells are arranged;

a plurality of memory areas which are arranged in the memory array and have a plurality of second nonvolatile memory cells in which the same predetermined information is stored;

a sequence circuit which generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on;

a write-read unit which writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal;

a latch circuit which latches the predetermined information which is read by the write-read unit, based on the latch selection signal; and

a selection-drive unit which selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.

2. The semiconductor nonvolatile memory of claim 1, wherein the memory areas are separated from the memory array by a selection transistor which is controlled by the selection-drive unit such that an erase operation and a write operation can independently be performed in the memory areas.

3. The semiconductor nonvolatile memory of claim 1 wherein a memory cell selecting word line or an information transmitting bit line, which is directly connected to each of the second nonvolatile memory cells provided in the memory areas, is not adjacent lines or the same line in the plurality of memory areas.

4. The semiconductor nonvolatile memory of claim 1, wherein the selection-drive unit comprises a built-in power supply circuit which generates a voltage applied to the first and second nonvolatile memory cells with reference to a supply voltage or a divided voltage of the supply voltage based on the predetermined information latched by the latch circuit in a read operation when the power is turned on by the supply voltage.

5. The semiconductor nonvolatile memory of claim 4, wherein

the built-in power supply circuit has a function of outputting information on a trimming target voltage or a trimming target reference current, and

the built-in power supply circuit outputs the information on the trimming target voltage or the trimming target reference current using an external terminal with predetermined specifications.

6. The semiconductor nonvolatile memory of claim 1, wherein

the first and second nonvolatile memory cells have a configuration in which information having a plurality of bits can be stored, and

the second nonvolatile memory cells store and use one-bit of information from the plurality of bits.

7. The semiconductor nonvolatile memory of claim 6, wherein the second nonvolatile memory cells comprise storage nodes of the plurality of bits, and use the storage nodes of the plurality of bits by using all of the storage nodes of the plurality of bits in a written state or an erased state.

8. The semiconductor nonvolatile memory of claim 1, wherein

the plurality of second nonvolatile memory cells respectively store logical information values of both 0 and 1 as the predetermined information,

the sequence circuit comprises a determination unit,

the determination unit

carries out repeated cycles of reading the plurality of second nonvolatile memory cells through the write-read unit in a read operation when the power is turned on,

determines whether or not all of the read logical values are matched with the logical information values, and

causes the write-read unit to read the predetermined information when all of the read logical values are matched with the logical information values.

9. The semiconductor nonvolatile memory of claim 8, wherein a trimming logical value is changed until a determination result by the determination unit is matched.

10. The semiconductor nonvolatile memory of claim 8, wherein the plurality of memory areas are sequentially read until a determination result by the determination unit is matched.

11. The semiconductor nonvolatile memory of claim 1, wherein

the sequence circuit comprises a determination unit,

the determination unit

reads the predetermined information which is stored in each of the plurality of second nonvolatile memory cells and carries out a computation on the read predetermined information in a read operation when the power is turned on,

after reading all of the predetermined information, compares the computed predetermined information and information which is read through the write-read unit and which was computed and written in advance when the predetermined information was written to the second nonvolatile memory cell, and

reads the predetermined information of the second nonvolatile memory cells through the write-read unit until the comparison result of both the computed information match.

12. The semiconductor nonvolatile memory of claim 1, wherein

the sequence circuit comprises an output stop unit, and

the output stop unit stops outputting a read logical value of the predetermined information, which is read from the plurality of second nonvolatile memory cells through the write-read unit, to a chip output terminal in a read operation when the power is turned on.

13. The semiconductor nonvolatile memory of claim 1, wherein the write-read unit combines a plurality of information storage areas and read logical values of a plurality of area specification bits to form the predetermined information stored in the second nonvolatile memory cells, and causes the latch circuit to latch the predetermined information.

14. The semiconductor nonvolatile memory of claim 1, wherein the latch circuit is arranged adjacent to the selection-drive unit.

15. The semiconductor nonvolatile memory of claim 1, wherein the sequence circuit has a read access time which is longer than an access time defined by specifications in a read operation when the power is turned on.

16. The semiconductor nonvolatile memory of claim 1, wherein the predetermined information to be latched by the latch circuit is inputted from a chip external terminal irrespective of a logical value of the second nonvolatile memory cells in which the predetermined information is stored.