Dynamic power control of a memory device thermal sensor

• US 20080043556A1
• Filed: 08/01/2006
• Published: 02/21/2008
• Est. Priority Date: 08/01/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nale, William H.
• Granted Patent: US 8,272,781 B2
• Time in Patent Office: Days
• US Class Current: 365/212
• CPC Class Codes: G01K 7/425 Thermal management of integrated systems
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/3034 where the computing system component is a storage system, e.g. DASD based or network based digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3093 Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the on-die thermal sensor senses thermal data responsive to a thermal data sense indication. The thermal data sense indication may be received subsequent to the expiration of a delay period.

Claims

1. A memory device comprising:

enable logic to receive an enable indication from a host and to dynamically provide an enable signal to power-on an on-die thermal sensor; and

an on-die thermal sensor coupled with the enable logic, wherein the on-die thermal sensor is to sense thermal data responsive to a thermal data sense indication, the thermal data sense indication to be received subsequent to the expiration of a delay period.

2. The memory device of claim 1, wherein the enable logic comprises:

a storage element to store the enable indication.

3. The memory device of claim 2, wherein the enable logic further comprises:

an enable circuit to provide the enable signal to the on-die thermal sensor.

4. The memory device of claim 3, wherein the enable circuit is configured to receive, as an input, the enable indication.

5. The memory device of claim 4, wherein the thermal data sense indication is a memory interconnect impedance calibration command.

6. The memory device of claim 5, wherein the memory interconnect impedance calibration command is a ZQ calibration command.

7. The memory device of claim 2, wherein the enable indication comprises one or more bits of a mode register set (MRS) command.

8. The memory device of claim 7, wherein the storage element is at least a portion of a multipurpose register.

9. The memory device of claim 1, wherein the delay period corresponds to a set-up time of the on-die thermal sensor.

10. A method comprising:

receiving an enable indication to power-on an on-die thermal sensor;

generating a thermal data enable signal responsive, at least in part, to the enable indication;

receiving, subsequent to the expiration of a delay period, a thermal data sense indication; and

sensing the thermal data responsive, at least in part, to the thermal data sense indication.

11. The method of claim 10, wherein the enable indication comprises one or more bits of a mode register set (MRS) command.

12. The method of claim 10, wherein the delay period is associated with a thermal sensor set-up time.

13. The method of claim 10, wherein the thermal data sense indication is a memory interconnect impedance calibration command.

14. The method of claim 13, wherein the memory interconnect impedance calibration command is a ZQ calibration command.

15. The method of claim 10, further comprising:

receiving an indication to enter a multipurpose register read mode; and

providing the thermal data to a host from the multipurpose register.

16. The method of claim 15, further comprising:

receiving a disable indication to power-off an on-die thermal sensor.

17. A system comprising:

a controller;

a dynamic random access memory (DRAM) coupled with the host, the memory device including,

enable logic to receive an enable indication from a host and to dynamically provide an enable signal to power-on an on-die thermal sensor; and

an on-die thermal sensor coupled with the enable logic, wherein the on-die thermal sensor is to sense thermal data responsive to a thermal data sense indication, the thermal data sense indication to be received subsequent to the expiration of a delay period.

18. The system of claim 17, wherein the controller comprises:

thermal sensor control logic to determine when the on-die thermal sensor senses thermal data.

19. The system of claim 17, wherein, the DRAM is an element of a memory module.

20. The system of claim 19, wherein the memory module comprises:

thermal sensor control logic to determine when the on-die thermal sensor senses thermal data.

21. The system of claim 17, wherein the enable logic comprises:

a storage element to store the enable indication; and

an enable circuit to provide an enable signal to the on-die thermal sensor.

22. The system of claim 21, wherein the enable circuit is configured to receive, as an input, the enable indication and the thermal data sense indication.

23. The system of claim 22, wherein the thermal data sense indication is a memory interconnect impedance calibration command.

24. The system of claim 23, wherein the memory interconnect impedance calibration command is a ZQ calibration command.

25. The system of claim 21, wherein the enable indication comprises one or more bits of a mode register set (MRS) command.

26. The system of claim 21, wherein the storage element is at least a portion of a mode register.