Memory power management

• US 20080043559A1
• Filed: 08/18/2006
• Published: 02/21/2008
• Est. Priority Date: 08/18/2006
• Status: Active Grant

• Current Assignee: III Holdings 1, LLC (Intellectual Ventures LLC)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Granted Patent: US 7,619,945 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

Memory power management is described. A non-volatile memory array is provided, the array including separately controlled memory blocks. At least two charge pumps are coupled to the array, the charge pumps being configured to provide at least two voltages. Logic is configured to control how the voltages are delivered to the memory blocks.

Claims

1. A memory power management system, comprising:

a non-volatile rewritable memory array including a plurality of logical partitions, the memory array being configured in at least one memory plane that is fabricated above circuitry components;

at least two charge pumps coupled to the non-volatile rewritable memory array, wherein one charge pump provides a positive voltage and another charge pump provides a negative voltage; and

logic configured to control delivery of the voltages generated by the at least two charge pumps to each logical partition such that each logical partition is controlled independently of each other logical partition.

2. The memory power management system of claim 1, wherein the circuitry components includes the logic.

3. The memory power management system of claim 1, wherein the at least one memory plane is configured as a two-terminal, cross-point memory array.

4. The memory power management system of claim 3, wherein the at least one memory plane includes at least two memory planes that are vertically-stacked.

5. The memory power management system of claim 4, wherein each logical partition includes physical portions from multiple planes.

6. The memory power management system of claim 1, wherein the circuitry components include the at least two charge pumps.

7. The memory power management system of claim 1, wherein the memory array includes memory cells, each memory cell having an electrolytic tunnel barrier and a mixed valence conductive oxide.

8. The memory power management system of claim 1, wherein

the memory array is configured in at least two sub-planes, the sub-planes being configured to receive voltages generated by the at least two charge pumps;

and

the logic selects which sub-plane receives which voltage for each partition.

9. A memory power management system, comprising:

a memory being configured into one or more memory planes, each memory plane having a plurality of memory blocks wherein each memory block includes a plurality of memory elements;

a charge pump circuit coupled to the memory, the charge pump circuit being configured to deliver at least two voltages; and

a logic circuit coupled to the charge pump circuit and the memory, the logic circuit being configured to control the memory by, for each memory block, selecting one of the plurality of memory elements and directing one of the at least two voltages delivered by the charge pump circuit to the selected memory elements.

10. The memory power management system of claim 9, wherein the charge pump circuit includes exactly two charge pumps.

11. The memory power management system of claim 9, wherein the memory is a non-volatile memory array.

12. The memory power management system of claim 9, wherein the memory is a non-volatile, two-terminal, cross-point, third dimension memory array.

13. The memory power management system of claim 12, wherein the charge pump circuit is vertically disposed relative to the memory.

14. The memory power management system of claim 12, wherein the charge pump circuit and the logic circuit are vertically disposed relative to the memory.

15. The memory power management system of claim 12, wherein

each memory block includes memory cells, each memory cell having an electrolytic tunnel barrier and a mixed valence conductive oxide;

and

at least one of the at least two voltages, when applied to a memory cell, changes a conductivity profile of the memory cell.

16. A method for managing memory power, comprising:

providing a memory array having sub-planes, the memory array including a plurality of partitions;

providing a negative voltage;

providing a positive voltage;

selecting whether a sub-plane is to receive the positive voltage for each logical partion;

selecting whether a sub-plane is to receive the negative voltage for each logical partion; and

simultaneously gating the positive and negative voltages to the appropriate sub-plane.

17. The method of claim 16, wherein the memory array is non-volatile.

18. The method of claim 16, wherein the memory array is a non-volatile, vertically-stacked, cross-point memory array.

19. The method of claim 16, wherein the memory array is a third dimension memory array.

20. The method of claim 16, wherein the memory array includes memory cells, each memory cell having an electrolytic tunnel barrier and a mixed valence conductive oxide.