Memory power management
First Claim
Patent Images
1. A memory power management system, comprising:
- a non-volatile rewritable memory array including a plurality of logical partitions, the memory array being configured in at least one memory plane that is fabricated above circuitry components;
at least two charge pumps coupled to the non-volatile rewritable memory array, wherein one charge pump provides a positive voltage and another charge pump provides a negative voltage; and
logic configured to control delivery of the voltages generated by the at least two charge pumps to each logical partition such that each logical partition is controlled independently of each other logical partition.
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Abstract
Memory power management is described. A non-volatile memory array is provided, the array including separately controlled memory blocks. At least two charge pumps are coupled to the array, the charge pumps being configured to provide at least two voltages. Logic is configured to control how the voltages are delivered to the memory blocks.
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Citations
20 Claims
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1. A memory power management system, comprising:
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a non-volatile rewritable memory array including a plurality of logical partitions, the memory array being configured in at least one memory plane that is fabricated above circuitry components; at least two charge pumps coupled to the non-volatile rewritable memory array, wherein one charge pump provides a positive voltage and another charge pump provides a negative voltage; and logic configured to control delivery of the voltages generated by the at least two charge pumps to each logical partition such that each logical partition is controlled independently of each other logical partition. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory power management system, comprising:
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a memory being configured into one or more memory planes, each memory plane having a plurality of memory blocks wherein each memory block includes a plurality of memory elements; a charge pump circuit coupled to the memory, the charge pump circuit being configured to deliver at least two voltages; and a logic circuit coupled to the charge pump circuit and the memory, the logic circuit being configured to control the memory by, for each memory block, selecting one of the plurality of memory elements and directing one of the at least two voltages delivered by the charge pump circuit to the selected memory elements. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method for managing memory power, comprising:
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providing a memory array having sub-planes, the memory array including a plurality of partitions; providing a negative voltage; providing a positive voltage; selecting whether a sub-plane is to receive the positive voltage for each logical partion; selecting whether a sub-plane is to receive the negative voltage for each logical partion; and simultaneously gating the positive and negative voltages to the appropriate sub-plane. - View Dependent Claims (17, 18, 19, 20)
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Specification