FLEXIBLY CONTROLLING THE TRANSFER OF DATA BETWEEN INPUT/OUTPUT DEVICES AND MEMORY

• US 20080043563A1
• Filed: 08/15/2006
• Published: 02/21/2008
• Est. Priority Date: 08/15/2006
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Brice, Frank W., Bullions, Robert J., Elliot, Joseph C., Huang, Catherine C., Flanagan, John R., Sittmann, Gustav E., Casper, Daniel F., Gardiner, Mark P.
• Application Number:
  US11/464,613
• Publication Number:
  US 20080043563A1
• Time in Patent Office: Days
• US Class Current: 365/230.03
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

Data transfer between input/output devices and memory is controlled. Data transfer begins under the control of one control block, and control of the data transfer is passed from the one control block to another control block, in response to transferring an amount of data specified in the one control block. The passing of control occurs independent of a memory boundary, providing flexibility in controlling the data transfer. Each control block includes fields that control and facilitate the data transfer.

Claims

1. A method of controlling data transfers of a processing environment, said method comprising:

commencing a data transfer at a memory address specified in one control block; and

passing control of the data transfer to another control block, in response to transferring an amount of data specified in the one control block independent of a specific memory boundary.

2. The method of claim 1, wherein said one control block comprises a count indicating the amount of data to be transferred, said count being independent of a memory boundary.

3. The method of claim 1, further comprising determining whether additional data is to be transferred, and wherein the passing is in further response to the determining indicating additional data is to be transferred.

4. The method of claim 3, wherein said determining comprises comparing a count of the one control block with a count of a command word associated with the one control block to determine whether additional data is to be transferred.

5. The method of claim 1, wherein the another control block includes an address in memory to be used in the transfer, said address designating a block of memory not on a specific memory boundary and discontiguous to a block of memory designated by the one control block.

6. The method of claim 1, further comprising determining, in response to the another control block receiving control, whether data transfer for a range of memory specified by the another control block is to be skipped, said determining employing an indicator of the another control block.

7. The method of claim 1, wherein the one control block and the another control block are included within a list of control blocks, and further comprising verifying that the list of control blocks to be used in the data transfer includes enough control blocks to transfer a specified amount of data.

8. The method of claim 7, wherein the specified amount of data is included in a command word associated with the list of control blocks, and wherein the verifying employs an indicator of at least one control block of the list of control blocks.

9. The method of claim 1, wherein the one control block and the another control block are included in a list of control blocks, said list of control blocks including at least the one control block and the another control block, and said list of control blocks being specified by a command word of a program to facilitate the data transfer, the data transfer being between one or more input/output devices and noncontiguous memory.

10. The method of claim 1, wherein the data transfer proceeds uninterrupted by handshaking overhead between a channel and a control unit of the processing environment.

11. A system of controlling data transfers of a processing environment, said system comprising:

one control block having a memory address designating a location at which data transfer is to begin; and

another control block to receive control of the data transfer from the one control block, in response to an amount of data specified in the one control block being transferred, independent of a memory boundary.

12. The system of claim 11, wherein said one control block comprises a count to be compared with a count of a command word associated with the one control block to determine whether additional data is to be transferred.

13. The system of claim 11, wherein the another control block includes an address in memory to be used in the transfer, said address designating a block of memory not on a specific memory boundary and discontiguous to a block of memory designated by the one control block.

14. The system of claim 11, wherein the another control block includes an indicator used, in response to the another control block receiving control, to determine whether data transfer for a range of memory specified by the another control block is to be skipped.

15. The system of claim 11, wherein the one control block and the another control block are included within a list of control blocks, and wherein at least one control block of the list of control blocks includes an indicator used to verify that the list of control blocks to be used in the data transfer includes enough control blocks to transfer a specified amount of data.

16. An article of manufacture comprising:

at least one computer usable medium having computer readable program code logic to control data transfers of a processing environment, the computer readable program code logic comprising;

commence logic to commence a data transfer at a memory address specified in one control block; and

pass logic to pass control of the data transfer to another control block, in response to transferring an amount of data specified in the one control block independent of a memory boundary.

17. The article of manufacture of claim 16, further comprising logic to determine whether additional data is to be transferred, and wherein the passing is in further response to the determining indicating additional data is to be transferred.

18. The article of manufacture of claim 16, wherein the another control block includes an address in memory to be used in the transfer, said address designating a block of memory not on a specific memory boundary and discontiguous to a block of memory designated by the one control block.

19. The article of manufacture of claim 16, further comprising logic to determine, in response to the another control block receiving control, whether data transfer for a range of memory specified by the another control block is to be skipped, said logic employing an indicator of the another control block.

20. A channel program comprising:

a channel command word specifying a list of a plurality of modified indirect data address words usable in transferring data, wherein a modified indirect data address word comprises a memory address and a count field, and wherein data transfer begins at the memory address of one modified indirect data address word in the list and control of the data transfer passes to another modified indirect data address word in the list, in response to an amount of data specified in the count field of the one modified indirect data address word being transferred independent of a memory boundary.