Transmission using multiple physical interface

• US 20080043742A1
• Filed: 05/21/2007
• Published: 02/21/2008
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ning, Chun, Pong, Fong
• Granted Patent: US 8,718,065 B2
• Time in Patent Office: Days
• US Class Current: 370/394
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/70 Virtual switches

Abstract

A method to transmit data using a device having a plurality of physical input/output (I/O) interfaces is provided. The method comprises receiving data and determining a topology according to which data is to be transmitted. Data is transmitted in sequential order via a single physical interface for a first topology and in random order via a plurality of physical interfaces for a second topology.

A System On Chip (SOC) unit enabled to transmit data via one or more physical interfaces is provided. The SOC comprises a processor and a network interface including multiple physical input/output (I/O) interfaces coupled to the processor. In response to receiving data for transmission, the processor is enabled to select a single I/O interface for sequential data transmission according to a first topology or select multiple physical I/O interfaces for random order data transmission according to a second topology.

Claims

1. A computer program product comprising a computer useable medium including control logic stored therein to transmit data via one or more physical interfaces of a communications device, comprising:

control logic means for causing a processor to receive data from an application;

control logic means for causing a processor to determine a topology according to which data is to be transmitted;

control logic means for causing a processor to transmit data sequentially via a single physical interface for a first network topology; and

control logic means for causing a processor to transmit data in random order via a plurality of physical interfaces for a second network topology.

2. The computer program product of claim 1, further comprising control logic means for causing the processor to use a fragmenter and synchronizer module to partition data into a plurality of packets prior to transmission according to the second network topology.

3. The computer program product of claim 2, further comprising control logic means for causing the processor to transmit the plurality of packets in a plurality of packet streams via the plurality of physical interfaces.

4. The computer program product of claim 3, further comprising control logic means for causing the processor to instruct the fragmenter and synchronizer module to transmit a synchronization message at the end of each of the plurality of packet streams.

5. The computer program product of claim 4, wherein a synchronization message associated with a packet stream indicates termination of the associated packet stream and enables a receiving device receiving to re-assemble the plurality of packet streams.

6. The computer program product of claim 1, wherein the first network topology is a Peripheral Component Interconnect (PCI) topology.

7. The computer program product of claim 1, wherein the second network topology is a Cache Coherent Non Uniform Memory Access (CCNUMA) or a clustering topology.

8. The computer program product of claim 7, wherein the communications device is a System on Chip (SOC) unit including a node controller and a packet manager.

9. The computer program product of claim 8, wherein data is transmitted in random order in response to a cache coherence command issued by the node controller.

10. A method of transmitting data using a device having a plurality of physical interfaces, comprising:

receiving data;

determining a topology according to which data is to be transmitted;

transmitting data in sequential order via a single physical interface for a first topology; and

transmitting data in random order via a plurality of physical interfaces for a second topology.

11. The method of claim 10, wherein the first topology is a Peripheral Component Interconnect (PCI) topology and the second topology is a Cache Coherent Non Uniform Memory Access (CCNUMA) or a clustering topology.

12. The method of claim 10, further comprising selecting a virtual interface to map data to one or more physical interfaces.

13. The method of claim 12, further comprising determining a mapping between the virtual interface and the one or more physical interfaces based on the determined topology.

14. The method of claim 10, further comprising framing data into multiple packets for transmission via multiple physical interfaces for the second topology.

15. The method of claim 14, further comprising scheduling the packets prior to transmission via the multiple physical interfaces for the second topology.

16. The method of claim 15, further comprising transmitting synchronization messages associated with packets streams transmitted via the plurality of physical interfaces.

17. A method of transmitting data in a System on Chip (SOC) unit having multiple physical interfaces, comprising:

receiving a packet;

determining a protocol to transmit the packet;

determining a virtual interface to transmit the packet;

determining a mapping between the virtual interface and the multiple physical interfaces;

transmitting the packet via a single physical interface for a first protocol; and

transmitting the packet via a plurality of physical interfaces for a second protocol.

18. The method of claim 17, wherein the first protocol is a Peripheral Component Interconnect (PCI) protocol and the second protocol is a Cache Coherent Non Uniform Memory Access (CCNUMA) protocol.

19. The method of claim 18, further comprising framing data into multiple packets prior to transmitting the multiple packets via the multiple physical interfaces for the second protocol.

20. A System On Chip (SOC) unit, comprising:

a processor; and

a network interface including multiple physical input/output (I/O) interfaces coupled to the processor;

wherein in response to receiving data for transmission, the processor is enabled to select a single I/O interface for sequential data transmission according to a Peripheral Component Interconnect (PCI) topology or select multiple physical I/O interfaces for random order data transmission according to a Cache Coherent Non Uniform Memory Access (CCNUMA) or a clustering topology.

21. The SOC of claim 20, wherein the network interface is enabled to partition the data into packets and transmit the packets via the multiple physical I/O interfaces for the CCNUMA or the clustering topology.