System and Method for Clock Domain Management

• US 20080043752A1
• Filed: 08/18/2006
• Published: 02/21/2008
• Est. Priority Date: 08/18/2006
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Mohrmann, Leonard E. III
• Granted Patent: US 8,966,308 B2
• Time in Patent Office: Days
• US Class Current: 370/395.62
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

A source clock system clock domain is selected by communication of the desired clock domain from a receiver clock system through a clock line, such as through a clock differential pair. For instance, the source clock system signals available clock domains by selectively altering the polarity of a first clock line of the pair and the receiver clock system selects from the available clock domains by altering the polarity of a second clock line of the pair. Polarity is altered by selectively interfacing a resistor with the clock lines and then removing the resistor interface when the clock signal associated with the selected clock domain is sent by the source clock system.

Claims

1. A method for managing a clock domain of a clock supporting communication of information between plural information handling system components over a bus, the method comprising:

selectively interfacing a ground with a clock line at a clock receiver to request a desired clock domain from a clock source;

receiving the request at the clock source;

removing the ground interface with the clock line; and

applying the requested clock domain to the clock line with the clock source for use by the clock receiver.

2. The method of claim 1 further comprising:

selectively interfacing a ground with a clock line at the clock source to indicate available clock domains to the clock receiver.

3. The method of claim 1 wherein the clock domain comprises spread spectrum signaling.

4. The method of claim 1 wherein the clock domain comprises a data driven clock.

5. The method of claim 1 wherein the clock domain comprises a precision clock.

6. The method of claim 1 wherein the bus comprises a serialize data link.

7. The method of claim 1 wherein the clock source comprises a differential pair of clock lines operable to provide a clock signal to the clock receiver.

8. The method of claim 7 further comprising:

adding parasitic loading to the clocks for supporting communication of the clock signal.

9. A system for managing a clock domain of a clock supporting communication of information between plural information handling system components over a bus, the system comprising:

a source clock system operable to provide a clock signal to one or more clock lines, the clock signal selectable from plural clock domains;

a receiver clock system operable to receive the clock signal from the clock lines;

a clock domain requester associated with the receiver clock system, the clock domain requester operable to selectively alter the polarity of a clock line to communicate a clock domain request through the clock line; and

a clock domain selector associated with the source clock system, the clock domain selector operable to receive the clock domain request through the clock line and to select the clock signal associated with the requested clock domain to the one or more clock lines.

10. The system of claim 9 wherein the clock signal comprises a spread spectrum signal.

11. The system of claim 9 wherein the clock signal comprises a predetermined frequency.

12. The system of claim 9 wherein the clock signal comprises a precision clock signal.

13. The system of claim 9 wherein the clock signal comprises a data driven clock signal.

14. The system of claim 9 wherein the clock domain requester selectively alters the polarity of the clock line by selectively interfacing a resistor with the clock line.

15. The system of claim 9 wherein the clock domain selector is further operable to selectively alter the polarity of a clock line at the clock source to indicate available clock domains to the clock receiver.

16. The system of claim 15 wherein the clock domain selector selectively alters the polarity of the clock line at the clock source by selectively interfacing a resistor with the clock line at the clock source.

17. An information handling system comprising:

plural processing components operable to process information;

at least one bus operable to communicate information between at least two of the processing components, the bus communicating the information in accordance with a clock signal;

a source clock system associated with the bus and operable to selectively provide plural clock domains, each clock domain having an associated clock signal; and

a receiver clock system associated with the bus and operable to communicate a desired clock domain to the source clock system for selection of the associated clock signal.

18. The information handling system of claim 17 wherein the bus comprises a clock differential pair to communicate the clock signal and wherein the receiver clock system communicates the desired clock domain by selectively interfacing a resistor with the clock differential pair.

19. The information handling system of claim 18 wherein the bus comprises a PCI Express bus.

20. The information handling system of claim 17 wherein the source clock system is further operable to communicate available clock domains to the receiver clock system.