BODY-CONTACTED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTED SEMICONDUCTOR STRUCTURES

• US 20080044959A1
• Filed: 10/26/2007
• Published: 02/21/2008
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Hsu, Louis, Mandelman, Jack
• Granted Patent: US 7,608,506 B2
• Time in Patent Office: Days
• US Class Current: 438/155
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

Claims

1. A method for forming a semiconductor structure in a semiconductor wafer including a semiconductor substrate, a semiconductor layer including a plurality of semiconductor bodies, and a buried dielectric layer separating the semiconductor substrate from the semiconductor layer, the method comprising:

forming a plurality of trenches in the semiconductor wafer;

building a plurality of vertical memory cells each in a corresponding one of the trenches; and

forming a body contact that extends substantially through the buried dielectric layer and electrically couples one of the semiconductor bodies with the semiconductor substrate.

2. The method of claim 1 wherein forming the body contact further comprising:

implanting ions that stop in a region of the buried dielectric layer between two of the trenches to define the at least one body contact.

3. The method of claim 2 wherein the buried dielectric layer is a buried oxide layer containing silicon and oxygen in a first stoichiometry, and implanting ions further comprises:

implanting silicon ions into the region of buried oxide layer to provide a second stoichiometry in the implanted region that differs from the first stoichiometry.

4. The method of claim 3 wherein an implanted dose of silicon ions is sufficient to sufficient to provide a second stoichiometry including about 1 atomic percent to about 6 atomic percent of silicon in excess of the first stoichiometry of the buried oxide layer.

5. The method of claim 1 wherein the vertical memory cells further include a first vertical memory cell and a second vertical memory cell adjacent to the first vertical memory cell, and further comprising:

forming an insulating layer on the semiconductor body;

building a plurality of word lines on the semiconductor wafer including a first word line on the insulating layer between the first and second memory cells and electrically isolated from the first and second memory cells; and

removing a portion of the first word line to provide a body contact opening that exposes an area of the insulating layer overlying a region in the buried dielectric layer in which the body contact is subsequently formed.

6. The method of claim 5 wherein forming the at least one body contact further comprises:

implanting ions into the region in the buried dielectric layer through the body contact opening.

7. The method of claim 6 wherein the implanted ions penetrate through the insulating layer area and an area of the semiconductor body registered vertically with the insulating layer area to reach the buried dielectric layer region.

8. The method of claim 7 wherein implanting ions further comprises:

selecting a kinetic energy of the implanted ions such that the implanted ions stop predominantly in the buried dielectric layer underlying the removed portion of the first word line to define the at least one body contact.

9. The method of claim 5 wherein the word lines further include a second word line connected with an access device of the first vertical memory cell and a third word line connected with an access device of the second vertical memory cell, the second and third word lines electrically isolated from the first word line.

10. The method of claim 1 wherein each of the vertical memory cells including a storage capacitor and an access device with a vertical channel defined in the semiconductor body and a gate configured to switch current flow through the vertical channel to the storage capacitor.