High performance system-on-chip using post passivation process
First Claim
Patent Images
1. A integrated circuit chip comprising:
- a silicon substrate;
a transistor in or on said silicon substrate;
a first metal layer over said silicon substrate;
a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a first metal pad over said silicon substrate, wherein said first metal pad has a top surface with a first region and a second region surrounding said first region;
a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer is on said second region, and a first opening in said passivation layer is over said first region, wherein said first opening exposes said first region, wherein said first opening has a transverse dimension smaller than that of said first metal pad and between 0.5 and 30 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;
a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness greater than those of said passivation layer and said dielectric layer and has a thickness between 2 and 150 μ
m;
a metal post in said first polymer layer, wherein said metal post is connected to said first metal pad through said first opening, and wherein said metal post has a height and a transverse dimension, wherein said height is greater than said transverse dimension;
a coil over said first polymer layer, wherein said coil is connected to said first metal pad through said metal post and said first opening; and
a metal line over said first polymer layer, wherein said metal line is separate from said coil; and
a second polymer layer over said metal line.
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Abstract
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
121 Citations
20 Claims
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1. A integrated circuit chip comprising:
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a silicon substrate;
a transistor in or on said silicon substrate;
a first metal layer over said silicon substrate;
a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a first metal pad over said silicon substrate, wherein said first metal pad has a top surface with a first region and a second region surrounding said first region;
a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer is on said second region, and a first opening in said passivation layer is over said first region, wherein said first opening exposes said first region, wherein said first opening has a transverse dimension smaller than that of said first metal pad and between 0.5 and 30 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;
a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness greater than those of said passivation layer and said dielectric layer and has a thickness between 2 and 150 μ
m;
a metal post in said first polymer layer, wherein said metal post is connected to said first metal pad through said first opening, and wherein said metal post has a height and a transverse dimension, wherein said height is greater than said transverse dimension;
a coil over said first polymer layer, wherein said coil is connected to said first metal pad through said metal post and said first opening; and
a metal line over said first polymer layer, wherein said metal line is separate from said coil; and
a second polymer layer over said metal line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A integrated circuit chip comprising:
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a silicon substrate;
a transistor in or on said silicon substrate;
a first metal layer over said silicon substrate;
a second metal layer over said first metal layer;
a dielectric layer between said first and second metal layers;
a first metal pad over said silicon substrate, wherein said first metal pad has a top surface with a first region and a second region surrounding said first region;
a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer is on said second region, and a first opening in said passivation layer is over said first region, wherein said first opening exposes said first region, wherein said first opening has a transverse dimension smaller than that of said first metal pad and between 0.5 and 30 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;
a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness greater than those of said passivation layer and said dielectric layer and has a thickness between 2 and 150 μ
m,a coil over said first polymer layer, wherein said coil is connected to said first metal pad through said first opening;
a metal line over said first polymer layer, wherein said metal line is separate from said coil;
a second polymer layer over said metal line;
a contact pad over said second polymer layer, wherein said contact pad is connected to said metal line. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification