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High performance system-on-chip using post passivation process

  • US 20080044977A1
  • Filed: 10/23/2007
  • Published: 02/21/2008
  • Est. Priority Date: 12/21/1998
  • Status: Abandoned Application
First Claim
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1. A integrated circuit chip comprising:

  • a silicon substrate;

    a transistor in or on said silicon substrate;

    a first metal layer over said silicon substrate;

    a second metal layer over said first metal layer;

    a dielectric layer between said first and second metal layers;

    a first metal pad over said silicon substrate, wherein said first metal pad has a top surface with a first region and a second region surrounding said first region;

    a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer is on said second region, and a first opening in said passivation layer is over said first region, wherein said first opening exposes said first region, wherein said first opening has a transverse dimension smaller than that of said first metal pad and between 0.5 and 30 micrometers, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer;

    a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness greater than those of said passivation layer and said dielectric layer and has a thickness between 2 and 150 μ

    m;

    a metal post in said first polymer layer, wherein said metal post is connected to said first metal pad through said first opening, and wherein said metal post has a height and a transverse dimension, wherein said height is greater than said transverse dimension;

    a coil over said first polymer layer, wherein said coil is connected to said first metal pad through said metal post and said first opening; and

    a metal line over said first polymer layer, wherein said metal line is separate from said coil; and

    a second polymer layer over said metal line.

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