SEMICONDUCTOR DEVICE CAPABLE OF THRESHOLD VOLTAGE ADJUSTMENT BY APPLYING AN EXTERNAL VOLTAGE

• US 20080044994A1
• Filed: 10/24/2007
• Published: 02/21/2008
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: Jin Ahn, Jun Cho, Sang Lee, Sung Park, Yil Kim
• Original Assignee: Jin Ahn, Jun Cho, Sang Lee, Sung Park, Yil Kim
• Inventors: LEE, Sang, KIM, Yil, CHO, Jun, PARK, Sung, AHN, Jin
• Granted Patent: US 7,449,392 B2
• Time in Patent Office: Days
• US Class Current: 438/595
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A semiconductor device has a silicon substrate, in which an active region is formed between two device isolation films and a gate is formed on the surface of the active region. The silicon substrate has a laterally etched portion in the active region below the surface of the active region on the side near the device isolation film. An insulating film is formed on the laterally etched portion of the silicon substrate. A conductive electrode is formed on the insulating film, through which an external voltage is applied to adjust a threshold voltage. The device isolation film is formed on the conductive electrode. None or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.

Claims

1. A method of manufacturing a semiconductor device having gates and junction regions, the method comprising the steps of:

forming a pad oxide film and a pad nitride film on a silicon substrate having a device isolation region and an active region;

etching the pad oxide film, the pad nitride film, and the silicon substrate to form a trench in the device isolation region;

forming an insulating film spacer on a trench sidewall including the etched pad oxide and nitride films;

laterally etching a portion of the active region in the silicon substrate using the pad oxide film, the pad nitride film, and the insulating film spacer as etch barriers;

removing the insulating film spacer;

forming a conductive electrode on the surface adjoining the laterally etched portion in the active region and on the surface of the trench in the isolation region; and

filling up the trench and the laterally etched portion with an oxide film to form a device isolation film, wherein none or some pockets of vacant cavity is present between the device isolation film and the conductive electrode.

2. The method of claim 1, wherein the step of etching the pad oxide and nitride film is performed using a gas mixture of CF₄/CHF₃/O₂.

3. The method of claim 2, wherein the flow rates of the CF₄, CHF₃ and O₂ gases are 10 to 100 sccm, 10 to 300 sccm and 10 to 70 sccm, respectively.

4. The method of claim 1, wherein the step of etching the silicon substrate to form the trench is performed using a gas mixture of Cl₂/HBr.

5. The method of claim 4, wherein the flow rates of the CL₂ and HBr gases are 10 to 100 sccm, respectively.

6. The method of claim 1, wherein the trench is formed with a depth of 1000 to 3000 Å

.

7. The method of claim 1, further comprising the step of performing heat treatment at the temperature of 800 to 1000°

C. under a hydrogen atmosphere after the step of forming the insulating film spacer and before the step of laterally etching a portion within the active region of the silicon substrate.

8. The method of claim 1, wherein the step of laterally etching a portion in the active region of the silicon substrate is performed by any one of (1) a dry etch process using plasma, (2) a wet etch process using chemicals and (3) a dry etch process using a gas mixture of elements from Group VII including F, Cl, Br and hydrogen.

9. The method of claim 1, wherein the step of laterally etching a portion in the active region of the silicon substrate is performed using a gas mixture of HCl and H₂.

10. The method of claim 8, wherein the flow rates of the HCl and H₂ gases are 0.1 slm and 10 to 50 slm, respectively.

11. The method of claim 9, wherein the step of laterally etching a portion in the active region of the silicon substrate is performed at a temperature of 700 to 1000°

C.

12. The method of claim 1, further comprising the step of performing field stop implantation onto the substrate surface of the exposed trench bottom surface after the step laterally etching a portion in the active region of the silicon substrate and before the step of removing the insulating film spacer.

13. The method of claim 1, wherein the step of forming the conductive electrode comprises the steps of:

forming an insulating film on the surface of the trench in the isolation region including the surfaces of the pad oxide and nitride films and on the surface of the laterally etched portion in the active region;

forming a electrode material film on the insulating film;

etching-back the electrode material formed in the trench on the surfaces of the pad oxide and nitride films exposing a portion of the insulating film; and

removing the exposed portion of the insulating film.

14. The method of claim 13, wherein the insulating film is an SOG film or a photoresist film.

15. The method of claim 13, wherein the step of etching-back the electrode material is performed using a gas mixture of Cl₂/HBr.

16. The method of claim 15, wherein flow rate of the CL₂ and HBr gases are 10 to 100 sccm, respectively.

17. The method of claim 13, wherein the step of etching-back the electrode material is performed using a solution mixture of acetic acid, nitric acid and NH₃OH.

18. The method of claim 1, wherein the gate is formed such that a multi-layer structure of a gate oxide film, a gate conductive film and a hard mask film is provided and the gate has gate spacers in both sidewalls thereof.