Post passivation interconnection schemes on top of IC chip
First Claim
1. A method for fabricating a chip, comprising:
- providing a silicon substrate and an interconnecting structure over said silicon substrate, wherein said interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and
forming a power bus over said silicon substrate, wherein said forming said power bus comprises;
forming a first metal layer, after said forming said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer.
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Accused Products
Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
115 Citations
16 Claims
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1. A method for fabricating a chip, comprising:
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providing a silicon substrate and an interconnecting structure over said silicon substrate, wherein said interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and
forming a power bus over said silicon substrate, wherein said forming said power bus comprises;
forming a first metal layer, after said forming said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for fabricating a chip, comprising:
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providing a silicon substrate, a first internal circuit in or on said silicon substrate, and a second internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit, and a passivation layer over said dielectric layer; and
forming a power bus and a polymer layer over said passivation layer, wherein said power bus is in said polymer layer, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said power bus and said second interconnecting structure, and wherein said forming said power bus comprises;
forming a first metal layer, after said forming said first metal layer, forming a patterned photoresist layer, after said forming said patterned photoresist layer, electroplating a second metal layer, after said electroplating said second metal layer, removing said patterned photoresist layer, and after said removing said patterned photoresist layer, etching said first metal layer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification