RFID READER SYSTEMS WITH DIGITAL RATE CONVERSION

• US 20080046492A1
• Filed: 01/11/2007
• Published: 02/21/2008
• Est. Priority Date: 05/19/2006
• Status: Abandoned Application

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Sundstrom, Kurt E.
• Application Number:
  US11/622,140
• Publication Number:
  US 20080046492A1
• Time in Patent Office: Days
• US Class Current: 708/200
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H04L 7/0029 interpolation of received data signal

Abstract

Fractional delay based digital rate conversion is employed for timing recovery from RFID tag responses at an RFID reader. Signal received from the tag is asynchronously sampled and interpolated. A desired time variant fractional delay coefficient is computed based on the interpolation and time offset is adjusted such that an output sample matches a target point. A data matched filter is optionally integrated with the fractional delay based digital rate converter, which includes a digital phase lock loop.

Claims

1. A method for an RFID reader system using digital rate conversion for timing recovery, the method comprising:

receiving a tag response signal waveform;

obtaining sample values of the tag response signal waveform at sample time points;

reconstructing signal values at target time points from the sample values by computing a desired time variant fractional delay;

outputting the reconstructed signal values; and

further processing the output signal values.

2. The method of claim 1, further comprising:

reconstructing an output signal from the output signal values.

3. The method of claim 1, in which

at least one of the target time points substantially corresponds to a zero crossing of the tag response signal waveform.

4. The method of claim 1, in which

at least one of the target time points substantially corresponds to a peak of the tag response signal waveform.

5. The method of claim 4, further comprising:

determining when the waveform peak occurs.

6. The method of claim 4, further comprising:

adjusting a time offset for the target time points such that one of the target time points substantially corresponds to the peak.

7. The method of claim 6, further comprising:

reconstructing the output signal from the offset target points.

8. The method of claim 4, in which

the desired time variant fractional delay is computed by interpolating over the sample time points followed by a decimation of the interpolated points for reaching the target time points.

9. The method of claim 8, in which

interpolating over time sample points includes performing one from a set:

of first order, second order, third order, and fourth order polynomial interpolation.

10. The method of claim 8, in which

interpolating over the sample points includes performing a Lagrange interpolation.

11. The method of claim 8, further comprising:

employing a Phase Locked Loop (PLL) to determine a time offset for the interpolated points.

12. The method of claim 11, in which

the PLL includes a loop filter and a Numerically Controlled Oscillator (NCO) configured to provide feedback to a timing processor for determination of the time offset for the interpolated points and time instants for the decimation.

13. The method of claim 12, further comprising:

monitoring an output of the NCO at the timing processor; and

updating a decimation point of the interpolated sample points in response to a roll-over of the NCO output.

14. The method of claim 12, further comprising:

computing a time offset coefficient at the timing processor for an interpolating filter performing the interpolation over the sample points.

15. The method of claim 11, further comprising:

filtering the target data points employing a data matched filter in the PLL.

16. An RFID reader system arranged to use digital rate conversion for timing recovery, comprising:

a receiver circuit configured to receive a tag response signal;

a signal processing circuit configured to;

receive a tag response signal waveform;

obtain sample values of the tag response signal waveform at sample time points;

reconstruct signal values at target time points from the sample values by computing a desired time variant fractional delay; and

output the reconstructed signal values.

17. The system of claim 16, further comprising:

one or more digital processing circuitry configured to process the output signal for further reader operations.

18. The system of claim 16, further composing:

a transmitter configured to transmit a carrier wave to a plurality of tags to elicit the tag response signal.

19. The system of claim 16, in which

the signal processing is further configured to reconstruct an output signal from the output signal values.

20. The system of claim 16, in which

at least one of the target time points substantially corresponds to a zero crossing of the tag response signal waveform.

21. The system of claim 16, in which

at least one of the target time points substantially corresponds to a peak of the tag response signal waveform.

22. The system of claim 21, in which

the signal processing is further configured to determine when the waveform peak occurs.

23. The system of claim 21, in which

the signal processing is further configured to adjust a time offset for the target time points such that one of the target time points substantially corresponds to the peak.

24. The system of claim 23, in which

the signal processing is further configured to reconstruct, the output signal from the offset target points.

25. The system of claim 21, in which

the desired time variant fractional delay is computed by interpolating over the sample time points followed by decimation of the interpolated points for reaching the target time points.

26. The system of claim 25, in which

the signal processing is further configured to interpolate over the sample points by perforating one from a set of first order, second order, third order, and fourth order polynomial interpolation.

27. The system of claim 25, to which

the signal processing is further configured to interpolate over the sample points by performing a Lagrange interpolation.

28. The system of claim 25, in which

the signal processing is further configured to employ a Phase Locked Loop (PLL) to determine a time offset for the interpolated time points.

29. The system of claim 21, in which

the PLL includes a loop filter and a Numerically Controlled Oscillator (NCO) configured to provide feedback to a timing processor for determination of the time offset for the interpolated points and time instants for the decimation.

30. The system of claim 29, in which

the signal processing is further configured to:

monitor an output of the NCO at the timing processor; and

update a decimation point of the interpolated sample points in response to a roll-over of the NCO output.

31. The system of claim 29, in which

the signal processing is further configured to compute a time offset coefficient, at the timing processor for an interpolating filter performing the interpolation over the sample points.

32. The system of claim 28, in which

the signal processing is further configured to filler the sample data points employing a data matched filter in the PLL.

33. The system of claim 16, wherein

the signal processing circuit is digital.

34. The system of claim 16, in which

the signal processing circuit is part of a Digital Signal Processor (DSP).

35. The system of claim 16, in which

the signal processing circuit is part of a Field Programmable Gate Array (FPGA),

36. A circuit for a Radio Frequency Identification (RFID) reader system, comprising:

a digital rate converter circuit arranged to;

obtain sample values of a tag response signal waveform at sample time points;

reconstruct signal values at target time points from the sample values by computing a desired time variant fractional delay; and

output the reconstructed signal values;

a phase detector coupled to the digital rate converter, the phase detector receiving an input signal that is also an output signal from the offset sample points;

a loop filter coupled to the phase detector;

a numerically controlled oscillator coupled to the loop filter and to the digital rate converter; and

a matched filter coupled to fee digital rate converter.

37. The circuit of claim 36, in which

at least one of the target time points substantially corresponds to a zero crossing of the tag response signal waveform.

38. The circuit of claim 36, in which

at least one of the target lime points substantially corresponds to a peak of the tag response signal waveform.

39. The circuit of claim 38, in which

the digital rate converter is further arranged to:

compute the desired time variant fractional delay by interpolating over the sample time points for reaching the target time points;

adjust a time offset for the target time points such that one of the target time points substantially corresponds to the peak; and

reconstruct the output signal from the offset target points.

40. The circuit of claim 36, in which

the matched filter is arranged to provide a signal to the digital rate converter, and the digital rate converter provides the output signal.

41. The circuit of claim 36, in which

the matched filter is coupled between the digital rate converter and the phase detector, and is arranged to provide the output signal.

42. The circuit of claim 36, in which

the digital rate converter includes:

an interpolating filter arranged to receive the sample time points, interpolate, and generate offset target points;

a first decimator coupled to the interpolating filler arranged to decimate a portion of the sample points such that offset sample points corresponding to the target, time points are provided by the digital rate converter; and

a timing processor arranged to provide the interpolating filter a time variant fractional delay coefficient and a decimation control signal to the first decimator based on an output of the numerically controlled oscillator.

43. The circuit of claim 36, in which

the phase detector includes:

a decimator arranged, to receive the input signal; and

a timing error detector coupled to the decimator arranged to provide a timing, correction signal to the loop filter.

49. The computer readable storage medium of claim 41, in which

at least one of the target time points substantially corresponds to a zero crossing of the tag response signal waveform.

44. An RFID reader system arranged to use digital rate conversion for timing recovery, comprising:

means for receiving a tag response signal waveform;

means for obtaining sample values of the tag response signal waveform at sample time points;

means for reconstructing signal values at target time points from the sample values by computing a desired time variant fractional delay;

means for outputting the reconstructed signal values; and

means for further processing the output signal values.

45. The system of claim 44, further comprising:

means for determining when the waveform peak occurs, wherein at least one of the target time points substantially corresponds to a peak of the tag response signal waveform.

46. The system of claim 45, further comprising:

means for adjusting a time offset for the target time points such that one of the target time points substantially corresponds to the peak.

47. The system of claim 46, further comprising:

means for reconstructing the output signal from the offset target points, wherein the desired time variant fractional delay is computed by interpolating over the sample time points for reaching the target time points.

48. A computer readable storage medium for an RFID reader system with instructions stored thereon for performing digital rate conversion for timing recovery, the instructions comprising:

receiving a tag response signal waveform;

obtaining sample values of the tag response signal waveform at sample time points;

reconstructing signal values at target time points from the sample values by computing a desired time variant fractional delay;

outputting the reconstructed signal values; and

further processing the output signal values.

50. The computer readable storage medium of claim 48, in which

at least one of the target time points substantially corresponds to a peak of the tag response signal waveform, and

the instructions further comprise:

determining when the waveform peak occurs.

51. The computer readable storage medium of claim 50, in which

the instructions farther comprise:

adjusting a time offset for the target time points such that one of the target time points substantially corresponds to the peak.

52. The computer readable storage medium of claim 51, in which

the desired time variant fractional delay is computed by interpolating over the sample time points for reaching the target time points, and

the instructions further comprise:

reconstructing the output signal from the offset target points.

53. The computer readable storage medium of claim 52, in which

a number of the target time points is determined based on a type of interpolation to be performed over the sample points.