SYSTEMS AND METHODS FOR PROGRAM DIRECTED MEMORY ACCESS PATTERNS

• US 20080046666A1
• Filed: 08/15/2006
• Published: 02/21/2008
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Termaine, Robert B.
• Granted Patent: US 7,539,842 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.

Claims

1. A computer memory system for storing and retrieving data, the system comprising:

a memory including a plurality of memory devices organized into one or more physical groups, wherein each group is accessible via an associated bus for transferring data and control information;

a memory controller for receiving and responding to memory access requests that include application access information to control access pattern and data organization within the memory, the responding including accessing one or more memory devices in one or more of the physical groups via the associated busses; and

a virtual memory management system including a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory and also including a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory, and a means for conveying the hint state to the memory controller when a memory access request is directed to the memory controller to access the memory.

2. The system of claim 1, wherein the responding further includes selecting which of the associated busses will be used to satisfy the memory access request responsive to the physical memory organization conveyed to the memory controller in the hint state.

3. The system of claim 1, wherein the responding further includes selecting which error detection and correction logic will be utilized to protect data integrity, the selection responsive to the physical memory organization state conveyed to the memory controller in the hint state.

4. The system of claim 1, wherein the responding further includes grouping multiple pending memory access requests for optimal memory throughput by servicing pending requests from pending or queued requests which have complementary interleave attributes at the same time.

5. The system of claim 1, wherein the virtual memory management system transmits a page table entry associated with the memory access request to the memory controller.

6. The system of claim 1, wherein the virtual memory management system specifies hint states in the page table entries, the specifying responsive to memory allocation requests to the memory.

7. The system of claim 1, wherein the responding further includes generating and checking error correction codes for information transferred on the associated busses, wherein the generating is performed on data being written to one or more memory devices and the checking is performed on data being read from one or more memory devices.

8. A memory system comprising:

a plurality of busses for transferring information to memory devices; and

a memory controller in communication with the busses for receiving memory access requests and for initiating an information transfer on one or more of the busses to respond to the memory access requests, wherein the memory controller determines on a cycle by cycle basis which of the busses are required to respond to each of the memory access requests based on a memory access pattern associated with each memory access request.

9. The memory system of claim 8 wherein any unused busses for one of the memory access requests may be utilized concurrently to perform an other of the memory access requests.

10. The memory system of claim 8, further comprising a virtual address translation table (VATT) which includes an address range and an access hint defined by an operating system (OS), wherein the access hint affects all subsequent memory access requests to the address range, the access hint can be changed by the OS during system operation, and the access hint is utilized by the memory controller to determine which of the busses are required to satisfy the memory access request.

11. The memory system of claim 10 wherein the access hint includes the one or more busses required to satisfy the memory access request for the address range.

12. The memory system of claim 10 wherein the access hint includes a preferred access granularity for the address range.

13. The memory system of claim 10 wherein the VATT includes entries defining how virtual addresses are mapped to real addresses on the memory devices.

14. The memory subsystem of claim 8 wherein a memory error correction code (ECC) generation and checking circuit is operable across one or more of the busses.

15. The memory subsystem of claim 8 wherein one or more of system software and a VATT provides information about what ECC encode and decode circuits are to be utilized to support the memory access request.

16. The memory subsystem of claim 8 wherein the memory controller schedules memory accesses to maximize throughput based on bus utilization.

17. A method for processing a read request in a memory system, the method comprising:

receiving a read request including a virtual address;

completing a virtual address to real address mapping;

forwarding the real address to a memory controller that is in communication with a plurality of busses;

selecting one or more of the busses that are required to process the read request;

accessing just the required busses to process the read request;

reading data responsive to the read request from one or more memory devices attached to the required busses; and

transmitting the data to a requestor.

18. The method of claim 17 further comprising performing an ECC check on just the required busses.

19. The method of claim 17 wherein the selecting is responsive to an access hint associated with the virtual address.

20. The method of claim 17 wherein two or more memory access requests are processed concurrently by the memory system via the busses.

21. A method for processing a write request in a memory system, the method comprising:

receiving a write request including application access information at a memory controller that is in communication with a plurality of busses;

selecting one or more of the busses that are required to process the write request, the selecting responsive to the application access information;

accessing just the required busses to process the write request; and

writing data responsive to the write request to one or more memory devices attached to the required busses.

22. The method of claim 21 further comprising creating an ECC code for just the busses required to process the write request.

23. The method of claim 21 further comprising processing one or more of a read request that requires a different set of busses than the write request or a second write request that requires a different set of busses than the write request in parallel with the write request.