Synchronization clocking scheme for small scalable multi-processor system

• US 20080046770A1
• Filed: 07/05/2007
• Published: 02/21/2008
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: MiTAC International Corporation (MiTAC Holdings Corp.)
• Original Assignee: TYAN Computer Corp. (MiTAC Holdings Corp.)
• Inventors: Jong, Jyh Ming, Hirai, Tomonori
• Granted Patent: US 7,870,413 B2
• Time in Patent Office: Days
• US Class Current: 713/375
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL. The distribution-clock path and the self-clock path will have equal lengths, making the base clock pass through the two connectors or the same connector twice to achieve the similar electrical characteristics and balance the skew or propagation delay

Claims

1. A clocking scheme for a multi-processor system, the multi-processor system having at least two independent SMP (Symmetric Multi-Processing) domains and an interconnection board connecting with any two of the SMP domains, the clocking scheme comprising:

a clock source located on each of the SMP domains, generating a base clock and sending to each of the SMP domains;

a SPLL (Select Phase-Locked Loop) located on each of the SMP domains, receiving at least one of the base clocks from at least one of the SMP domains, and selecting one of the base clocks according to a select signal to generate an N-times faster clock;

a clock buffer located on each of the SMP domains, providing duplicated copies of the N-times faster clock to a plurality of processors located at the same SMP domain; and

a self-clock path sending the base clock to the SPLL on the same SMP domain;

wherein at least one of the base clocks is sent through a distribution-clock path to another of the SPLLs on another of the SMP domains, the distribution-clock path and the self-clock path having equal lengths.

2. The clocking scheme of claim 1, wherein each of the self-clock path and the distribution-clock path comprises a start segment on the SMP domain of start, an interconnection segment on the interconnection board, and an end segment on the SMP domain of destination.

3. The clocking scheme of claim 2, wherein the self-clock path and the distribution-clock path from the same clock source comprises equal lengths at the start segment, interconnection segment and end segment.

4. The clocking scheme of claim 2, wherein all the self-clock paths and the distribution-clock paths in the multi-processor system comprises equal lengths at the start segment, interconnection segment and end segment.

5. The clocking scheme of claim 1, wherein the select signal is generated by a glue logic.

6. The clocking scheme of claim 5, wherein the glue logic is located on each of the SMP domains or the interconnection board.

7. The clocking scheme of claim 5, wherein the glue logic generates the select signal according to a configuration signal that defines the SMP configuration of the multi-processor system.

8. The clocking scheme of claim 1, wherein the interconnection board connects with at least two of the SMP domains through at least two identical connectors, each of the distribution-clock path and the self-clock path passing through the two connectors or through the same connector twice.

9. The clocking scheme of claim 1 further comprising a multiplexer located on at least one of the SMP domains for sending the base clock through the distribution-clock path and the self-clock path.

10. A multi-processor system comprising:

at least two independent SMP (Symmetric Multi-Processing) domains;

an interconnection board connecting with any two of the SMP domains; and

a clocking scheme for clocking synchronization across the SMP domains, comprising;

a clock source located on each of the SMP domains, generating a base clock and sending to each of the SMP domains;

a SPLL (Select Phase-Locked Loop) located on each of the SMP domains, receiving at least one of the base clocks from at least one of the SMP domains, and selecting one of the base clocks according to a select signal to generate an N-times faster clock; and

a clock buffer located on each of the SMP domains, providing duplicated copies of the N-times faster clock to a plurality of processors located at the same SMP domain; and

a self-clock path sending the base clock to the SPLL on the same SMP domain;

wherein at least one of the base clocks is sent through a distribution-clock path to another of the SPLLs on another of the SMP domains, the distribution-clock path and the self-clock path having equal lengths.

11. The multi-processor system of claim 10, wherein each of the self-clock path and the distribution-clock path comprises a start segment on the SMP domain of start, an interconnection segment on the interconnection board, and an end segment on the SMP domain of destination.

12. The multi-processor system of claim 11, wherein the self-clock path and the distribution-clock path from the same clock source comprises equal lengths at the start segment, interconnection segment and end segment.

13. The multi-processor system of claim 11, wherein all the self-clock paths and the distribution-clock paths in the multi-processor system comprises equal lengths at the start segment, interconnection segment and end segment.

14. The multi-processor system of claim 10, wherein the select signal is generated by a glue logic.

15. The multi-processor system of claim 14, wherein the glue logic is located on each of the SMP domains or the interconnection board.

16. The multi-processor system of claim 14, wherein the glue logic generates the select signal according to a configuration signal that defines the SMP configuration of the multi-processor system.

17. The multi-processor system of claim 10, wherein the interconnection board connects with at least two of the SMP domains through at least two identical connectors, each of the distribution-clock path and the self-clock path passing through the two connectors or through the same connector twice.

18. The multi-processor system of claim 10 further comprising a multiplexer located on at least one of the SMP domains for sending the base clock through the distribution-clock path and the self-clock path.