SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING FAULT DETECTION AND CORRECTION IN A MEMORY SUBSYSTEM

• US 20080046796A1
• Filed: 09/07/2007
• Published: 02/21/2008
• Est. Priority Date: 10/29/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dell, Timothy, Maule, Warren, Gower, Kevin
• Granted Patent: US 8,140,942 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

Claims

1. A method for providing error detection and correction, the method comprising:

receiving an error code correction (ECC) word at a memory assembly in multiple packets via a memory bus, the ECC word including data bits and ECC bits arranged into multiple ECC symbols, each of the ECC symbols associated with one bitlane on the memory bus;

utilizing one of the ECC symbols to perform error detection and correction to bits in the ECC word received via the bitlane associated with the symbol;

creating a new ECC word with symbols; and

transmitting the new ECC word.

2. The method of claim 1 wherein the memory assembly is a memory controller or a memory module.

3. The method of claim 1 wherein the memory bus comprises twenty-two bitlanes.

4. The method of claim 3 wherein eighteen of the twenty-two bitlanes contain data bits and four of the twenty-two bitlanes contain the ECC bits.

5. The method of claim 1 wherein the receiving an ECC word requires four packets to be transferred via the memory bus.

6. The method of claim 1 wherein each of the ECC symbols includes four bits.

7. The method of claim 1 wherein the memory bus and the memory assembly are part of a cascaded interconnect memory system.

8. The method of claim 1 wherein the memory bus is a downstream bus.

9. The method of claim 1 wherein the memory bus is an upstream bus.

10. The method of claim 1 wherein each ECC symbol is four bits and the ECC word includes an 88/72 ECC code that will detect errors in the ECC symbol, correct errors in the ECC symbol and detect double symbol errors.

11. The method of claim 1 wherein the ECC bits are also data bits.