Highly integrated media access control

• US 20080046952A1
• Filed: 08/17/2007
• Published: 02/21/2008
• Est. Priority Date: 09/27/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Nazareth, Sean, Denney, Lisa, Pantelias, Niki, Lansing, Shane, Moshar, Hooman, Horton, John
• Granted Patent: US 7,835,398 B2
• Time in Patent Office: Days
• US Class Current: 725/125
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/52 by attributing bandwidth to queues
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

A supervisory communications device, such as a headend device within a communications network, monitors and controls communications with a plurality of remote communications devices throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A highly integrated media access controller integrated circuit (MAC IC) operates within the headend to provide lower level processing on signals exchanged with the remote devices. The enhanced functionality of the MAC IC relieves the processing burden on the headend CPU and increases packet throughput. The enhanced functionality includes header suppression and expansion, DES encryption and decryption, fragment reassembly, concatenation, and DMA operations

Claims

1. A method for processing signals within a media access controller integrated circuit (MAC IC), comprising:

receiving a signal from a physical layer device coupled to the MAC IC, the physical layer device operable for communication over a wireless medium;

pre-processing a header within the signal, the signal being prioritized or stored according to the header;

detecting a fragmented voice and/or data packet from the signal; and

reassembling fragmented frames to produce a reassembled voice and/or data packet in response to the detecting a fragmented voice and/or data packet.

2. The method of claim 1, further comprising:

checking a key sequence number to decrypt the signal.

3. The method of claim 2, further comprising:

retrieving a BPI key to decrypt the signal.

13. The method of claim 1, further comprising:

detecting a need for additional or fewer unsolicited grants, including the steps of;

reading a current unsolicited grant synchronization (“

UGS”

) EHDR from the signal; and

comparing the current UGS EHDR to a prior UGS EHDR to detect the need for additional or fewer unsolicited grants.

4. A method for processing ingress signals within a MAC IC, comprising:

receiving a downlink signal;

generating a header for the downlink signal, the header being added to the downlink signal; and

delivering the downlink signal to a physical layer device operable to wirelessly transmit the downlink signal to a remote device.

5. The method of claim 4, wherein generating a header comprises:

performing payload header suppression.

6. The method of claim 5, wherein performing payload header suppression comprises:

querying a downlink memory to fetch a payload header suppression/expansion (“

PHS”

) rule to perform the payload header suppression.

7. The method of claim 4, further comprising:

collecting statistics.

8. An integrated circuit for providing media access control, comprising:

an egress preprocessor for pre-processing an egress signal, wherein the egress preprocessor is configured to receive the egress signal from a physical layer device coupled to the integrated circuit, the physical layer device operable for communication over a wireless medium; and

a fragment reassembly controller configured to receive a fragmented voice and/or data packet detected from the egress signal, wherein the fragment reassembly controller is operable to reassemble the fragmented voice and/or data packet to generate a reassembled voice and/or data packet.

9. The integrated circuit of claim 8, further comprising:

an ingress processor for processing an ingress signal.

10. The integrated circuit of claim 9, wherein the ingress processor comprises:

a payload header suppression/expansion (“

PHS”

) processor for suppressing a payload header for the ingress signal.

11. A method of processing egress signals within a media access controller integrated circuit (MAC IC), comprising:

receiving a signal from a physical layer device coupled to the MAC IC, the physical layer device operable for communication over a wireless medium;

processing a header within the signal and prioritizing or storing the signal according to the header; and

expanding a payload header suppressed packet from the signal in response to detecting a suppressed header within the signal.

12. The method of claim 11, further comprising:

querying a payload header suppression/expansion (“

PHS”

) memory to retrieve a key to expand the payload header suppressed packet.

14. A method for processing ingress signals within a MAC IC, comprising:

receiving a downlink signal;

suppressing a payload header for a packet included in the downlink signal to thereby produce a suppressed header, the header being added to the downlink signal; and

delivering the downlink signal to a physical layer device operable to wirelessly transmit the downlink signal to a remote device.

15. The method of claim 14, further comprising:

processing the downlink signal to provide MPEG encapsulation.

16. The method of claim 14, further comprising:

interleaving the downlink signal with a MPEG video frame.

17. The method of claim 14, further comprising:

collecting statistics.

18. A integrated circuit for providing media access control, comprising:

an egress processor configured to receive an egress signal from a physical layer device coupled to the integrated circuit, the physical layer device operable to communicate over a wireless medium; and

a payload header suppression/expansion (“

PHS”

) processor configured to expand a payload header suppressed packet detected from the egress signal.

19. The integrated circuit of claim 18, wherein the egress processor comprises:

a fragment reassembly controller configured to receive a fragmented voice and/or data packet detected from the egress signal, and to reassemble the fragmented voice and/or data packet to produce a reassembled voice and/or data packet.

20. The integrated circuit of claim 18, further comprising:

memory controller means configured to support operations of the egress processor, and/or the fragment reassembly controller.

21. The integrated circuit of claim 20, further comprising:

memory controller means for supporting operations of the ingress processor.

22. A integrated circuit for providing media access control, comprising:

a header processor for accessing an ingress signal and producing a header for the ingress signal; and

a downstream PHY interface for delivering the ingress signal to a physical layer device operable to wirelessly transmit the downstream signal to a remote device.

23. The integrated circuit of claim 22, further comprising:

an MPEG encapsulator for producing a MPEG frame from the ingress signal.

24. The integrated circuit of claim 22, further comprising:

an encryptor for performing data encryption standard (“

DES”

) encryption on the ingress signal.

25. The integrated circuit of claim 22, further comprising:

direct memory access means for retrieving the ingress signal, and enabling the header processor to access the ingress signal.

26. The integrated circuit of claim 22, wherein the header processor generates a header checksum (“

HCS”

) and/or cyclic redundancy check (“

CRC”

) fields to enable error detection for the ingress signal.

27. A integrated circuit for providing media access control, comprising:

a payload header suppression/expansion (“

PHS”

) processor for accessing an ingress signal and suppressing a payload header for the ingress signal; and

a downstream PHY interface for delivering the ingress signal to a physical layer device operable to wirelessly transmit the downstream signal to a remote device.

28. The integrated circuit of claim 27, further comprising:

direct memory access means for retrieving the ingress signal, and enabling the header processor to access the ingress signal.

29. The integrated circuit of claim 27, wherein the header processor generates header checksum (“

HCS”

) and/or cyclic redundancy check (“

CRC”

) fields to enable error detection for the ingress signal.