Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frame

• US 20080048211A1
• Filed: 07/20/2007
• Published: 02/28/2008
• Est. Priority Date: 07/20/2006
• Status: Active Grant

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Khuri-Yakub, Butrus, Ergun, Arif, Zhuang, Xuefeng
• Granted Patent: US 7,741,686 B2
• Time in Patent Office: Days
• US Class Current: 257/204
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A one or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame is provided. The CMUT array has at least three array elements deposited on a conductive substrate. The invention also has at least one CMUT cell in the array element, a conductive top layer deposited to a top side of the element, and a conductive via disposed within the elements. The via is isolated from the conductive top layer and conducts with the substrate. There are at least two isolation trenches in the conductive substrate, and the trenches are disposed between adjacent vias to conductively isolating the vias. A substrate region between the trenches forms a mechanical support frame. At least one conductive electrode is deposited to a bottom surface of the conductive substrate, where the electrode conducts with the via. The support frame eliminates the need for a carrier wafer in the process steps.

Claims

1. A one-dimensional or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame comprising:

a. at least three CMUT array elements deposited on a conductive substrate;

b. at least one CMUT cell in said array element;

c. a conductive top layer deposited to a top side of said element;

d. a conductive via disposed within said elements, wherein said via is isolated from said conductive top layer and conducts with said substrate;

e. at least two isolation trenches in said conductive substrate, wherein said trenches are disposed between adjacent said vias, whereby conductively isolating said vias, whereas a substrate region between said trenches forms a mechanical support frame; and

f. at least one conductive electrode deposited to a bottom surface of said conductive substrate, wherein said electrode is disposed to conduct with said via.

2. The CMUT array with supporting frame of claim 1, wherein said conductive substrate comprises a silicon-on-insulator wafer, whereby said wafer comprises a silicon oxide layer on a silicon layer.

3. The CMUT array with supporting frame of claim 1, wherein said conductive top layer comprises a conductive material selected from a group consisting of aluminum, titanium, tungsten and polysilicon.

4. The CMUT array with supporting frame of claim 1, wherein said conductive top layer is omitted when said top side of said element comprises as highly conductive silicon membrane.

5. The CMUT array with supporting frame of claim 1, wherein said conductive via comprises a conductive material selected from a group consisting of aluminum, polysilicon and amorphous silicon.

6. The CMUT array with supporting frame of claim 1, wherein said conductive electrode is selected from a group consisting of copper, titanium, gold, platinum, aluminum and nickel.

7. A method of fabricating a one-dimensional or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame comprising:

a. providing a double-side-polished silicon-on-insulator wafer;

b. etching CMUT cavities in a device layer of said wafer using oxidation and buffered oxide etching methods;

c. electrically dividing front electrical pads on said wafer using deep reactive ion etching;

d. bonding a second said silicon-on-insulator wafer to said etched device layer;

e. removing a handle layer of said second silicon-on-insulator wafer;

f. providing a contact via on each array element of said CMUT array using photo lithography and wet etching or dry etching;

g. depositing a conductive top electrode material on said etched wafer;

h. removing said conductive material around said vias to separate front and back electrodes from each other;

i. etching through-wafer trenches on said silicon wafer for electrical isolation and to define a supporting frame;

j. patterning signal electrodes on said back electrodes; and

k. flip-chip bonding CMUT arrays to appropriate electronic circuits or printed circuit boards.

8. The method of claim 7, wherein said wafer bonding steps are replaced with sacrificial layer releasing steps.