Self-aligned, planar phase change memory elements and devices, systems employing the same and methods of forming the same

• US 20080048213A1
• Filed: 08/25/2006
• Published: 02/28/2008
• Est. Priority Date: 08/25/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Jun
• Granted Patent: US 7,910,905 B2
• Time in Patent Office: Days
• US Class Current: 257/246
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/828 Current flow limiting means within the switching material region, e.g. constrictions
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883

Abstract

Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width less than a width of a second portion of the phase change material layer. The first electrode, second electrode and phase change material layer may be oriented at least partially along a same horizontal plane.

Claims

1. A memory device comprising:

at least one memory element comprising;

first and second electrodes; and

a phase change material layer between the first and second electrodes, the phase change material layer having at least first, second and third portions, the first portion having a width less than the widths of the second and third portion.

wherein the second portion is in contact with the first electrode and the third portion is in contact with the second electrode, wherein the first portion is between the second and third portions, wherein the second portion is between the first electrode and the first portion, and wherein the third portion is between the second electrode and the first portion.

2. The memory device of claim 1, wherein the first and second electrodes are self aligned to the phase-change material layer.

3. The memory device of claim 1, wherein the first electrode, second electrode and phase change material layer are at least partially coplanar along a same horizontal plane.

4. The memory device of claim 3, wherein all of the first portion is encompassed between the first and second electrodes.

5. The memory device of claim 3, wherein the first portion is approximately centered between the first and second electrodes.

6. The memory device of claim 3, wherein a width of the phase change material layer progressively decreases from the second and third portions to the first portion.

7. The memory device of claim 3, wherein a width of the phase change material layer decreases in a step-wise manner from the second and third portions electrodes to the first portion.

8. The memory device of claim 3, wherein a width of the phase change material layer decreases linearly from the second and third portions to the first portion.

9. The memory device of claim 3, wherein the at least one memory element further comprises first and second dielectric layers between the first and second electrodes, and wherein the phase change material layer is vertically disposed between and in contact with the first and second dielectric layers.

10. The memory device of claim 1, further comprising at least one conductive plug, wherein the first electrode is in contact with the at least one conductive plug.

11. The memory device of claim 1, further comprising at least two memory elements and a conductive interconnect, wherein the conductive interconnect is in contact with second electrodes of the at least two memory elements.

12. A processor system comprising:

a processor coupled to a memory device, the memory device comprising;

a plurality of memory elements, at least two memory elements comprising;

a phase change material layer, and

first and second electrodes at opposing ends of the phase change material layer along a horizontal plane;

a dielectric layer over the at least two memory elements;

a conductive interconnect within the dielectric layer, the conductive interconnect in contact with the second electrodes of the at least two memory elements.

13. The system of claim 12, wherein a width of a first portion of the phase change material layer located between the first and second electrodes is less than each of a width of a second portion of the phase change material layer located adjacent the first electrode and a width of a third portion of the phase change material layer located adjacent the second electrode.

14. The system of claim 13, wherein the first portion is approximately centered between the first and second electrodes.

15. The system of claim 12, wherein the phase change material layer configured such that a programmable volume of the phase change material layer is spaced apart from the first and second electrodes.

16. The system of claim 12, wherein the conductive interconnect is self-aligned with the second electrodes of the at least two memory elements.

17. A memory element comprising:

first and second electrodes; and

a phase change material layer between the first and second electrodes, the phase change material layer configured such that a programmable volume of the phase change material layer is not in contact with the first or second electrodes.

18. The memory element of claim 17, wherein the first electrode, second electrode and phase change material layer are at least partially coplanar along a same horizontal plane.

19. The memory element of claim 18, further comprising first and second dielectric layers between the first and second electrodes, wherein the phase change material layer vertically disposed between and in contact with the first and second dielectric layers.

20. The memory element of claim 17, wherein the phase change material layer has first, second and third portions, the first portion having a width less than the widths of the second and third portions.

wherein the second portion is in contact with the first electrode and the third portion is in contact with the second electrode, wherein the first portion is between the second and third portions, wherein the second portion is between the first electrode and the first portion, and wherein the third portion is between the second electrode and the first portion.

21. The memory element of claim 20, wherein the first portion comprises the programmable volume.

22. The memory element of claim 20, wherein a width of the phase change material layer progressively decreases from the second and third portions to the first portion.

23. The memory element of claim 17, wherein the programmable volume is approximately centered between the first and second electrodes.

24. The memory element of claim 17, further comprising at least one conductive plug, wherein the first electrode is in contact with the at least one conductive plug.

25. The memory element of claim 17, wherein, the first and second electrodes are self-aligned to the phase change material layer.

26. A method of forming a memory element, the method comprising:

forming a first electrode;

forming a second electrode; and

forming at least one layer of phase change material between the first and second electrodes such that a programmable volume of the phase change material layer is spaced apart from the first and second electrodes.

27. The method of claim 26, wherein the first electrode, second electrode and phase change material layer are formed at least partially along a same horizontal plane

28. The method of claim 27, wherein the configuring step comprises etching a first portion of the phase change material to have a first width less than a width of the second portion of the phase change material layer.

29. The method of claim 28, wherein the first portion is approximately centered between the first and second electrodes.

30. The method of claim 27, wherein configuring step comprises etching the phase change material layer such that a width of the phase change material layer progressively decreases from points adjacent to the first and second electrodes to a point between the first and second electrodes.

31. A method of forming a memory device, the method comprising:

forming a first dielectric layer;

forming a layer of phase change material layer over the first dielectric layer;

forming a second dielectric layer over the phase change material layer;

forming a plurality of stacks by etching the first dielectric layer, the second dielectric layer and the phase change material layer, each stacks formed having sidewalls, the sidewalls including edges of the phase change material layer;

forming a first electrode on a first sidewall of each stack and in contact with a first edge of the phase change material layer;

forming a second electrode on a second sidewall of each stack and in contact with a second edge of the phase change material layer, the first sidewall being opposite the second sidewall; and

subsequent to forming the plurality of stacks, etching the phase change material layer of each stack such that, for each stack, a first portion of the phase change material layer has a first width less than a width of the second portion of the phase change material layer.

32. The method of claim 31, wherein the first portion is formed spaced apart from the first electrode.

33. The method of claim 31, wherein the first portion is formed spaced apart from the second electrode.

34. The method of claim 31, wherein the first portion is formed approximately centered between the first and second electrodes.

35. The method of claim 31, wherein the phase change material layer is etched such that a width of the phase change material layer progressively decreases from points adjacent to the first and second electrodes to the first portion.

36. The method of claim 31, wherein the phase change material layer is etched such that a width of the phase change material layer decreases in a step-wise manner from points adjacent to the first and second electrodes to the first portion.

37. The method of claim 31, wherein the phase change material layer is etched such that a width of the phase change material layer decreases linearly from points adjacent to the first and second electrodes to the first portion.

38. The method of claim 31, further comprising forming a plurality of conductive plugs, wherein each first electrode is formed in contact with a respective conductive plug.

39. The method of claim 31, further comprising:

forming a third dielectric layer over the stacks, first electrodes and second electrodes;

etching a via to expose two adjacent second electrodes; and

filling the via with a conductive material.