Semiconductor memory device having DRAM cell mode and non-volatile memory cell mode and operation method thereof

• US 20080048239A1
• Filed: 05/16/2007
• Published: 02/28/2008
• Est. Priority Date: 08/23/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yeo, In-Seok, Huo, Zong-Liang
• Granted Patent: US 7,982,256 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.

Claims

1. A semiconductor memory device, comprising:

a plurality of transistors arranged in an array on a semiconductor substrate, the transistors having floating bodies;

word lines connected to gate electrodes of the transistors;

bit lines connected to drains of the transistors at a first side of the gate electrodes;

source lines connected to sources of the transistors at a second side of the gate electrodes different from the first side of the gate electrodes; and

charge storage regions between the gate electrodes and the floating bodies.

2. The semiconductor memory device as claimed in claim 1, wherein each of the charge storage regions includes a dielectric layer.

3. The semiconductor memory device as claimed in claim 2, wherein the dielectric layer includes a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer.

4. The semiconductor memory device as claimed in claim 1, further comprising:

gate insulating layers between the floating bodies and the gate electrodes, and a buried insulating layer on the semiconductor substrate,

wherein each of the floating bodies is electrically isolated by the gate insulating layer, the buried insulating layer, the source, and the drain.

5. The semiconductor memory device as claimed in claim 1, further comprising:

gate insulating layers between the floating bodies and the gate electrodes;

a buried insulating layer on the semiconductor substrate; and

an isolation layer surrounding sidewalls of the floating body, wherein each of the floating bodies is electrically isolated by the gate insulating layer, the buried insulating layer, the isolation layer, the source, and the drain.

6. The semiconductor memory device as claimed in claim 1, wherein the source line is a common source line connected to sources of adjacent transistors.

7. The semiconductor memory device as claimed in claim 1, wherein the gate electrodes are on the floating bodies, and the sources and drains are at both sides of the floating bodies.

8. The semiconductor memory device as claimed in claim 1, wherein each of the floating bodies includes first and second floating bodies spaced apart from each other, the sources and drains being respectively under and on the first and second floating bodies, and the gate electrodes being between the first and second floating bodies.

9. The semiconductor memory device as claimed in claim 8, wherein the gate electrodes extend from their one ends to cross over the first and second floating bodies.

10. The semiconductor memory device as claimed in claim 8, further comprising:

back gate electrodes covering first sidewalls of the first and second floating bodies, wherein the gate electrodes include first and second gate electrodes insulated from each other, and the first and second gate electrodes cover second sidewalls of the first and second floating bodies, different from the first sidewalls.

11. The semiconductor memory device as claimed in claim 1, wherein each transistor in the array defines a memory cell, the device further comprising a selection circuit adapted to select at least one cell of the memory cells, to determine whether the selected cell is to operate in a DRAM cell mode or a non-volatile memory cell mode, and to operate the selected cell in the DRAM cell mode or the non-volatile memory cell mode in accordance with the determination.

12. The semiconductor memory device as claimed in claim 11, wherein, during operation of the selected cell in the DRAM cell mode, the selection circuit is adapted to:

apply a gate voltage to a gate electrode of the selected cell, gate electrodes of memory cells sharing a word line with the selected cell;

apply a drain voltage to a drain of the selected cell, drain electrodes of memory cells sharing a bit line with the selected cell; and

apply a source voltage lower than the drain voltage to a source of the selected cell, sources of memory cells sharing a source line with the selected cell to accumulate holes in the floating bodies.

13. The semiconductor memory device as claimed in claim 12, wherein the gate voltage is about 5V, the drain voltage is about 2V, and the source voltage is about 0V.

14. The semiconductor memory device as claimed in claim 11, wherein, during operation of the selected cell in the DRAM cell mode, the selection circuit is adapted to:

float a gate electrode of the selected cell, gate electrodes of memory cells sharing a word line with the selected cell;

apply a negative drain voltage to a drain of the selected cell, drains of memory cells sharing a bit line with the selected cell; and

apply a source voltage to a source of the selected cell, sources of memory cells sharing a source line with the selected cell to erase holes in the floating bodies.

15. The semiconductor memory device as claimed in claim 14, wherein the negative drain voltage is about −

2V, and the source voltage is about 0V.

16. The semiconductor memory device as claimed in claim 11, wherein, during operation of the selected cell in the non-volatile memory cell mode, the selection circuit is adapted to:

apply a gate voltage to a gate electrode of the selected cell, gate electrodes of memory cells sharing a word line with the selected cell;

apply a drain voltage to a drain of the selected cell, drains of memory cells sharing a bit line with the selected cell; and

apply a source voltage lower than the drain voltage to a source of the selected cell, sources of memory cells sharing a source line with the selected cell to store charges in the charge storage regions.

17. The semiconductor memory device as claimed in claim 16, wherein the gate voltage is about 10V, the drain voltage is about 5V, and the source voltage is about 0V.

18. The semiconductor memory device as claimed in claim 11, wherein, during operation of the selected cell in the non-volatile memory cell mode, the selection circuit is adapted to:

apply a negative gate voltage to a gate electrode of the selected cell, and gate electrodes of memory cells sharing a word line with the selected cell;

float a drain of the selected cell, and drains of memory cells sharing a bit line with the selected cell; and

apply a source voltage to a source of the selected cell, and sources of memory cells sharing a source line with the selected cell to erase charges in the charge storage regions.

19. The semiconductor memory device as claimed in claim 18, wherein the negative gate voltage is about −

8V, and the source voltage is about 0V.

20. A method of operating a semiconductor memory device having memory cells arranged in an array, each of the memory cells including a semiconductor substrate, a floating body disposed on the semiconductor substrate, a gate electrode insulated from the floating body, a source and a drain disposed in the semiconductor substrate at both sides of the gate electrode, and a charge storage region interposed between the floating body and the gate electrode, the method comprising:

selecting at least one cell of memory cells;

determining whether the selected sell is to operate in a DRAM cell mode or a non-volatile memory cell mode; and

operating the selected cell in the DRAM cell mode or the non-volatile memory cell mode, after determining an operational mode.