Lateral trench MOSFET with direct trench polysilicon contact and method of forming the same

• US 20080048251A1
• Filed: 08/28/2006
• Published: 02/28/2008
• Est. Priority Date: 08/28/2006
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Disney, Donald Ray, Ma, Cho Chiu
• Granted Patent: US 7,759,731 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched.

Claims

1. A lateral trench MOSFET comprising:

a semiconductor substrate;

a trench formed in the substrate, the trench being lined with a first dielectric layer and containing a conductive material, the first dielectric layer electrically insulating the conductive material from the substrate, the trench comprising an LTDMOS segment and a gate bus segment;

a body region of a first conductivity type abutting a sidewall of the LTDMOS segment of the trench;

a source region of second conductivity type positioned at a top surface of the substrate and adjoining the body region;

a drift region of the second conductivity type adjoining the body region and the sidewall of the LTDMOS segment of the trench;

a drain region of the second conductivity type adjoining the drift region and being positioned at the surface of the substrate at a location laterally spaced apart from the source region;

a second dielectric layer disposed above a top surface of the substrate, a contact hole being formed in the second dielectric layer over the gate bus segment of the trench; and

a gate metal layer above the second dielectric layer, the gate metal layer being in electrical contact with the conductive material in the gate bus segment of the trench via the contact hole.

2. The lateral trench MOSFET of claim 1 wherein a lateral dimension of the contact hole is located entirely over the gate bus segment of the trench.

3. The lateral trench MOSFET of claim 1 wherein the contact hole has substantially vertical sidewalls extending from a top surface of the second dielectric layer to the surface of the substrate.

4. The lateral trench MOSFET of claim 1 wherein the gate bus segment of the trench is wider than the LTDMOS segment of the trench.

5. The lateral trench MOSFET of claim 1 wherein a top surface of the conductive material in the trench is depressed with respect to the top surface of the substrate.

6. The lateral trench MOSFET of claim 5 comprising a third dielectric layer, the third dielectric layer being located in the trench between the top surface of the conductive material and the second dielectric layer.

7. A trench semiconductor device comprising:

a semiconductor substrate;

a trench formed in the substrate, the trench being lined with a first dielectric layer and containing a conductive material, the first dielectric layer electrically insulating the conductive material from the substrate, the trench comprising an device segment and a gate bus segment;

a second dielectric layer disposed above a top surface of the substrate, a contact hole being formed in the second dielectric layer over the gate bus segment of the trench, the contact hole having substantially vertical sidewalls, the sidewalls intersecting the conductive material in the gate bus segment of the trench;

a gate metal layer disposed above the second dielectric layer, the gate metal layer comprising a first metal; and

a conductive contact plug disposed in the contact hole, the contact plug providing electrical contact between the gate metal layer and the conductive material in the gate bus segment of the trench, the contact plug comprising a second metal different from the first metal.

8. The trench semiconductor device of claim 7 wherein a lateral dimension of the contact plug is located entirely over the gate bus segment of the trench.

9. The trench semiconductor device of claim 7 wherein the gate bus segment of the trench is wider than the device segment of the trench.

10. The trench semiconductor device of claim 7 wherein the trench is linear.

11. The trench semiconductor device of claim 8 wherein the linear trench comprises a plurality of gate bus segments disposed at regular intervals along the trench.

12. The trench semiconductor device of claim 11 wherein a gate bus segment is located at each end of the trench.

13. The trench semiconductor device of claim 7 wherein the trench is in the form of a closed loop.

14. The trench semiconductor device of claim 7 wherein a top surface of the conductive material in the trench is depressed with respect to the top surface of the substrate.

15. The trench semiconductor device of claim 14 comprising a third dielectric layer, the third dielectric layer being located in the trench between the top surface of the conductive material and the second dielectric layer.

16. The trench semiconductor device of claim 7 wherein the first metal comprises aluminum or an aluminum alloy.

17. The trench semiconductor device of claim 16 wherein the second metal comprises tungsten or a tungsten alloy.

18. The trench semiconductor device of claim 7 comprising a lateral trench MOSFET adjacent the device segment of the trench.

19. A semiconductor arrangement comprising:

a semiconductor substrate;

a trench formed in the substrate, the trench being lined with a first dielectric layer and containing a conductive material, the first dielectric layer electrically insulating the conductive material from the substrate, the trench comprising an device segment and a gate bus segment, a top surface of the conductive material in the trench being depressed with respect to the top surface of the substrate;

a first semiconductor device located adjacent the device segment of the trench;

a second dielectric layer disposed above a top surface of the substrate, a contact hole being formed in the second dielectric layer over the gate bus segment of the trench, the contact hole having substantially vertical sidewalls, the sidewalls intersecting the conductive material in the gate bus segment of the trench;

a gate metal layer above the second dielectric layer, the gate metal layer being in electrical contact with the conductive material in the gate bus segment of the trench via the contact hole;

a third dielectric layer, the third dielectric layer being located in the trench between the top surface of the conductive material and the second dielectric layer;

a shallow isolation trench formed in the substrate, the shallow isolation trench containing the third dielectric layer.

20. The semiconductor arrangement of claim 19 comprising a second semiconductor device adjacent the shallow isolation trench.

21. The semiconductor arrangement of claim 20 wherein the first device comprises a lateral trench MOSFET.

22. The semiconductor arrangement of claim 21 wherein the second device comprises a portion of a CMOS device.

23. A method of forming a lateral trench MOSFET comprising:

forming a trench in a semiconductor substrate, the trench comprising an LTDMOS segment and a gate bus segment;

lining the walls of the trench with a dielectric layer;

introducing a first conductive material into the trench;

implanting a dopant of a first conductivity type into the substrate to form a body region adjacent a sidewall of the LTDMOS segment of the trench;

implanting a dopant of a second conductivity type into the substrate to form a drift region adjacent the body region and the sidewall of the LTDMOS segment of the trench;

implanting a dopant of the second conductivity type into the substrate to form a source region adjacent a top surface of the substrate and the body region;

implanting a dopant of the second conductivity type into the substrate to form a drain region adjacent the top surface of the substrate laterally spaced apart from the source region;

forming a second dielectric layer over the top surface of the substrate;

forming a contact hole in the second dielectric layer above the gate bus segment of the trench, the contact hole having substantially vertical walls which intersect the conductive material in the gate bus segment of the trench;

filling the contact hole with a second conductive material to form a contact plug in the contact hole; and

forming a gate metal layer over the second dielectric layer, the gate metal layer being in contact with the contact plug.

24. The method of claim 23 comprising planarizing the top surfaces of the substrate and the first conductive material.

25. The method of claim 24 comprising forming and removing a protective layer over the substrate before the formation of the source and drain regions.

26. The method of claim 23 wherein filling the contact hole with a conductive material comprises filling the contact hole with tungsten.

27. A method of forming a semiconductor device comprising:

forming a first mask layer over the surface of a semiconductor substrate;

forming a first opening in the first mask layer;

etching the substrate through the first opening to form a first trench;

lining the walls of the first trench with a first dielectric layer;

introducing a first conductive material into the first trench;

forming a second mask layer over the first mask layer;

forming a second opening in the first and second mask layers;

removing the second mask layer;

introducing an etchant, the etchant etching the first conductive material through the first opening to form a recess in the first conductive material, the etchant etching the substrate through the second opening to form a second trench in the substrate;

forming a second dielectric layer over the top surface of the substrate, the second dielectric layer filling the recess in the first conductive material and the second trench; and

planarizing the second dielectric layer.

28. The method of claim 27 further comprising:

forming a first semiconductor device adjacent the first trench; and

forming a second semiconductor device adjacent the second trench.

29. The method of claim 28 wherein the first trench comprises a device segment and a gate bus segment, the method further comprising:

forming a third dielectric layer over the surface of the substrate;

forming a contact hole in the third dielectric layer, the hole having vertical walls which intersect the first conductive material in the gate bus segment of the first trench;

filling the contact hole with a second conductive material to form a contact plug in the contact hole; and

forming a gate metal layer over the second dielectric layer, the gate metal layer being in contact with the contact plug.

30. The method of claim 29 wherein the first device comprises a lateral trench MOSFET, the method further comprising:

implanting a dopant of a first conductivity type into the substrate to form a body region adjacent a sidewall of device segment of the trench;

implanting a dopant of a second conductivity type into the substrate to form a drift region adjacent the body region and the sidewall of the device segment of the trench;

implanting a dopant of the second conductivity type into the substrate to form a source region adjacent a top surface of the substrate and the body region; and

implanting a dopant of the second conductivity type into the substrate to form a drain region adjacent the top surface of the substrate laterally spaced apart from the source region.

31. The method of claim 30 further comprising:

forming a second opening in the first mask layer; and

etching the substrate through the second opening in the first mask layer to form a third trench in the substrate;

lining the walls of the third trench with a first dielectric layer; and

introducing the first conductive material into the third trench.