Strained semiconductor power device and method

• US 20080048257A1
• Filed: 08/25/2006
• Published: 02/28/2008
• Est. Priority Date: 08/25/2006
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Baird, Robert W., de Fresart, Edouard D.
• Granted Patent: US 7,651,918 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 438/912 Displacing pn junction

Abstract

Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a first semiconductor material (66) of a first conductivity type and a first lattice constant spaced apart by a gap or trench (69), filling (108, 210, 308) the trench or gap (69) with a second semiconductor material (70) of a second, conductivity type and a second different lattice constant so that the second semiconductor material (70) is strained with respect to the first semiconductor material (66) and forming (110, 212, 312) device regions (80, 88, S, G, D) communicating with the first (66) and second (70) semiconductor materials and adapted to provide device current (87, 87′) through at least part of the strained second semiconductor material (70) in the trench (69). In a preferred embodiment, the relaxed semiconductor material is 80:20 Si:Ge and the strained semiconductor material is substantially Si.

Claims

1. A method for forming a semiconductor (SC) device embodying a strained semiconductor, comprising:

providing a substrate;

forming over the substrate a relaxed semiconductor region having an outer surface and a trench therein extending from the outer surface to the substrate;

filling the trench with a strained semiconductor material;

providing device regions proximate the outer surface and the trench adapted to direct device current through the strained semiconductor material in the trench to the substrate.

2. The method of claim 1, further comprising:

prior to the forming step, providing a transition layer adapted to lie between an upper surface of the substrate and the relaxed semiconductor region and having a first lattice spacing adjacent the upper surface of the substrate and a second different lattice spacing adjacent the relaxed semiconductor region.

3. The method of claim 2, wherein the first lattice spacing substantially matches the lattice spacing of the upper surface of the substrate and the second lattice spacing substantially matches the lattice spacing of the relaxed semiconductor region.

4. The method of claim 1 wherein the relaxed semiconductor region comprises SiGe and the strained semiconductor material is substantially silicon.

5. The method of claim 4, wherein the substrate is single crystal silicon and the relaxed semiconductor region comprises SiGe in a ratio in the range of about 90:

10 to 60;

40 Si;

Ge.

6. The method of claim 5, further comprising:

prior to the forming step, providing a transition layer between the substrate and the relaxed semiconductor region having a Si;

Ge composition ration of about 100;

0 adjacent the substrate and about 80;

20 adjacent the relaxed semiconductor region.

7. The method of claim 1, wherein the step of providing device regions proximate the outer surface and the trench, comprises:

providing spaced-apart source regions in spaced apart portions of the relaxed semiconductor lying on either side of the trench at the outer surface;

providing a gate dielectric on the outer surface extending between the source regions; and

providing a gate overlying the gate dielectric and the trench at the outer surface.

8. The method of claim 7, further comprising, providing a drain contact on the substrate for receiving device current originating from the source regions and flowing through the strained semiconductor material in the trench.

9. A semiconductor device, comprising:

a substrate;

first and second relaxed semiconductor regions located on the substrate and separated by a trench extending from the substrate to an upper surface of the first and second relaxed semiconductor regions;

strained semiconductor material filling the trench between the first and second relaxed semiconductor regions, in contact with the substrate and having an upper end proximate the upper surface of the first and second relaxed semiconductor regions;

spaced-apart source regions located proximate the upper surface on either side of the upper end of the trench;

gate dielectric above the upper surface, extending at least between the spaced-apart source regions over the upper end of the trench;

a gate over the gate dielectric;

a drain contact coupled to the substrate;

wherein device current flowing from the sources to the substrate in response to signals applied to the gate, passes through the strained semiconductor material.

10. The device of claim 9, wherein the relaxed semiconductor regions comprise SiGe and the strained semiconductor consists substantially of silicon.

11. The device of claim 10, further comprising:

a conductive transition region located between the substrate and the relaxed semiconductor regions, and having a composition adjacent the substrate whose lattice constant substantially matches that of the substrate and having a composition adjacent the relaxed semiconductor regions whose lattice constant substantially matches that of the relaxed semiconductor regions.

12. The device of claim 9, further comprising;

an overlap region of the strained semiconductor material overlying the upper surface and communicating with the trench, wherein the overlap region has an outer surface; and

wherein the spaced-apart source regions are formed in the overlap region and the gate dielectric lies above the outer surface.

13. The device of claim 9, further comprising:

spaced-apart doped body regions of opposite conductivity type to the strained semiconductor material located in the relaxed semiconductor regions on either side of the trench and extending to the upper surface; and

wherein the spaced-apart source regions are located in doped body regions.

14. A method for forming VDMOS devices, comprising:

providing a substrate having a first surface and a first composition at the first surface;

forming a transition layer having a composition at the first surface substantially matching the first composition and having a different second composition at a second surface opposed to the first surface;

forming a relaxed semiconductor on the second surface, having a composition substantially matching the second composition, having a third surface opposite the second surface, and having two spaced-apart portions separated by a trench extending from the third surface to the second surface;

providing a strained semiconductor in the trench in contact with the second surface and extending to a fourth surface substantially coplanar with the third surface or above and substantially parallel with the third surface; and

forming device regions with sources and a gate proximate the fourth surface and straddling the trench and a drain coupled to the substrate, adapted to cause device current to flow from the sources to the drain via the strained semiconductor in the trench.

15. The method of claim 14, wherein the relaxed semiconductor comprises SiGe with a Si:

Ge ratio in the range of about 90;

10 to 60;

40 and the strained semiconductor comprises silicon with negligible germanium therein.

16. The method of claim 15, wherein the Si:

Ge ratio is about 80;

20.

17. The method of claim 14, wherein:

the step of providing a strained semiconductor comprises, providing a strained semiconductor in the trench and in an overlap region extending over at least part of the two spaced-apart portions of the relaxed semiconductor, so that the fourth surface is above and substantially parallel with the third surface; and

the step of forming the device regions comprises, forming the sources in and the gate over the overlap region.

18. The method of claim 14, wherein:

the step of providing a strained semiconductor comprises, providing a strained semiconductor in the trench so that the fourth surface is substantially coplanar with the third surface; and

the step of forming the device regions comprises, forming the sources in and the gate over the third surface.

19. The method of claim 14. wherein the first composition at the first surface is substantially silicon and the second composition at the second surface is substantially SiGe with Si:

Ge ratio in the range of about 90;

10 to about 60;

40.

20. The method of claim 14, further providing a dislocation absorption layer between the transition layer and the relaxed and strained semiconductor, having substantially the same composition as the second composition.