SEMICONDUCTOR DEVICE HAVING HEATING STRUCTURE AND METHOD OF FORMING THE SAME

• US 20080048293A1
• Filed: 08/21/2007
• Published: 02/28/2008
• Est. Priority Date: 08/22/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Horii, Hideki
• Application Number:
  US11/842,183
• Publication Number:
  US 20080048293A1
• Time in Patent Office: Days
• US Class Current: 257/536
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

A semiconductor device includes a lower electrode including a bottom wall portion and a sidewall portion extending upwardly from the bottom wall portion, and an insulating layer located over a top edge surface of the sidewall portion of the lower electrode. The insulating layer includes a contact window which partially exposes the top edge surface of the sidewall portion of the lower electrode. The device further includes a heated pattern which contacts the partially exposed top edge surface of the sidewall portion of the lower electrode through the contact window of the insulating layer.

Claims

1. A semiconductor device comprising:

a lower electrode including a bottom wall portion and a sidewall portion extending upwardly from the bottom wall portion;

an insulating layer located over a top edge surface of the sidewall portion of the lower electrode, the insulating layer including a contact window which partially exposes the top edge surface of the sidewall portion of the lower electrode; and

a heated pattern which contacts the partially exposed top edge surface of the sidewall portion of the lower electrode through the contact window of the insulating layer.

2. The semiconductor device of claim 1, wherein a width of the contact window is less than a width of the heated pattern;

and

wherein a contact area between the heated pattern and the lower electrode is a product of a thickness of the sidewall portion and the width of the contact window.

3. The semiconductor device of claim 1, wherein the partially exposed top edge surface of the sidewall portion of the lower electrode extends in a direction which is perpendicular to a lengthwise direction of the heated pattern;

and

wherein a contact area between the heated pattern and the lower electrode is a product of a thickness of the sidewall portion and a width of the heated pattern.

4. The semiconductor device of claim 1, wherein the partially exposed top edge surface of the sidewall portion of the lower electrode extends in a direction which is parallel to a lengthwise direction of the heated pattern;

and

wherein a contact area between the heated pattern and the lower electrode is a product of a thickness of the sidewall portion and a width of the contact window.

5. The semiconductor device of claim 1, wherein the lower electrode is one of a plurality of lower electrodes each including a bottom wall portion and a sidewall portion extending upwardly from the bottom wall portion;

wherein an insulating layer includes a plurality of contact windows which partially expose the top edge surface of the sidewall portion of the plurality of lower electrodes, respectively; and

wherein the heated pattern contacts the plurality of lower electrodes through the plurality of contact windows, respectively.

6. The semiconductor device of claim 1, wherein the heated pattern is formed of a material including at least one of Sb, Te, and Se.

7. The semiconductor device of claim 1, wherein the lower electrode is formed of at least one selected from the group consisting nitrides with metal atoms, oxynitrides with metal atoms, C, Ti, Ta, TiAl, Zr, Hf, Mo, Al, Al—

Cu, Al—

Cu—

Si, Cu, W, TiW, and WSix,

wherein the nitrides with metal atoms comprises TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, and TaAlN,

wherein the oxynitrides with metal atoms comprises TiON, TiAlON, WON, and TaON.

8. The semiconductor device of claim 1, wherein the sidewall portion of the lower electrode is a closed line having a thickness of 1 to 20 nm.

9. The semiconductor device of claim 1, further comprising a upper electrode disposed on and aligned with the heated pattern.

10. The semiconductor device of claim 9, wherein the upper electrode is formed of at least one selected from the group consisting nitrides with metal atoms, oxynitrides with metal atoms, C, Ti, Ta, TiAl, Zr, Hf, Mo, Al, Al—

Cu, Al—

Cu—

Si, Cu, W, TiW, and WSix,

wherein the nitrides with metal atoms comprises TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, and TaAlN,

wherein the oxynitrides with metal atoms comprises TiON, TiAlON, WON, and TaON.

11. The semiconductor device of claim 1, further comprising:

a lower conductive pattern disposed below the lower electrode and extending lengthwise in a direction perpendicular to the heated pattern; and

a semiconductor diode interposed between the lower conductive pattern and the lower electrode.

12. The semiconductor device of claim 11, wherein the lower electrode and the semiconductor diode are aligned with each other.

13. The semiconductor device of claim 11, wherein the lower conductive pattern comprises at least one of polycrystalline silicon, silicides, and metals.

14. The semiconductor device of claim 5, further comprising:

a plurality of inner insulating patterns interposed between the bottom portion of the respective lower electrodes and the insulating layer; and

an external insulating pattern which electrically isolates the lower electrodes from each other,

wherein the partially exposed top edge surface of the sidewall portion of each lower electrode is lower than top surfaces of the inner insulating patterns and the external insulating pattern.

15. The semiconductor device of claim 1, further comprising:

a transistor disposed below the lower electrode and comprising a gate electrode extending lengthwise in a direction perpendicular to the heated pattern, and source/drain regions formed at opposite sides of the gate electrode.

16. The semiconductor device of claim 15, further comprising:

a source line extending lengthwise in a direction parallel to the gate electrode;

a source plug which connects the source region with the source line; and

a drain plug which connects the drain region with the lower electrode.

17. The semiconductor device of claim 1, wherein the insulating layer has a thickness of 20 to 200 Å

, and is formed of one of a material having a resistivity of at least 10×

10<sup>−

3</sup> Ω

cm.

18. The semiconductor device of claim 1, wherein the contact window has a depth of 5 to 1000 Å

, and has an aspect ratio of 0.0001 to 2.

19. A method of forming a semiconductor device, the method comprising:

forming an external insulating pattern with a gap region on a semiconductor substrate;

forming a lower electrode with a bottom wall portion and a sidewall portion in the gap region, the sidewall portion extending upwardly from the bottom portion;

forming an insulating layer with a contact window on the external insulating pattern, the contact window partially exposing the top edge surface of the sidewall portion of the lower electrode; and

forming a heated pattern on the insulating layer which contacts the partially exposed top edge surface of the sidewall portion of the lower electrode through the contact window.

20. The method of claim 19, further comprising, before the forming of the lower electrode, forming a semiconductor diode disposed in a lower portion of the gap region, wherein the lower electrode is formed over the semiconductor diode.

21. The method of claim 20, further comprising, before the forming of the external insulating pattern, forming a lower conductive pattern in or over the substrate, wherein the semiconductor diode is formed on the lower conductive pattern, and wherein a lengthwise direction of the heated pattern is perpendicular to a lengthwise direction of the lower conductive pattern.

22. The method of claim of 21, wherein the forming of the semiconductor diode comprising:

performing an epitaxial process to form a semiconductor layer filling the gap region, the epitaxial process using the lower conductive pattern as a seed layer;

etching back the semiconductor layer to form a semiconductor pattern exposing an upper sidewall of the gap region; and

sequentially implanting impurities of different conductivity types into the semiconductor layer to form the diode.

23. The method of claim 19, further comprising, before the forming of the external insulating pattern:

forming a transistor which includes a gate electrode extending perpendicular to the heated pattern and source/drain regions on opposite sides of the gate electrode; and

forming a drain plug which electrically connects the drain region of the transistor with the lower electrode.

24. The method of claim 19, further comprising, before the forming of the insulating layer, forming an inner insulating pattern on the bottom portion of the lower electrode to at least partially fill the gap region.

25. The method of claim 24, wherein the forming of the lower electrode and the inner insulating pattern comprises:

forming the lower electrode layer so as to cover the bottom wall and sidewall surfaces of the gap region;

forming an inner insulating layer on the lower electrode layer to fill the gap region; and

etching the inner insulating layer and the lower electrode layer to expose a top surface of the external insulating pattern.

26. The method of claim 25, wherein the lower electrode layer is formed using one of ALD (atomic layer deposition), MO-CV) (metal organic chemical vapor deposition), Thermal CVD, Biased CVD, Plasma CVD and ECR CVD.

27. The method of claim 25, wherein the lower electrode layer is formed to cover conformally the bottom and sidewall surfaces of the gap region with a thickness of 1 to 20 nm.

28. The method of claim 19, wherein the external insulating pattern is formed with a plurality of gap regions, and wherein a plurality of lower electrodes each including a bottom wall portion and a sidewall portion are formed in the respective gap regions, and wherein forming of the insulating layer comprises:

forming a layer of insulating material over the lower electrodes; and

patterning the layer of insulating material to form a plurality of contact windows which partially expose the top edge surface of the sidewall portion the plurality of lower electrodes, respectively.

29. The method of claim 19, wherein the external insulating pattern is formed with a plurality of gap regions, and wherein a plurality of lower electrodes each including a bottom wall portion and a sidewall portion are formed in the respective gap regions, and wherein forming of the insulating layer comprises:

forming a layer of insulating material over the lower electrodes; and

patterning the layer of insulating material to form a contact window which extends lengthwise in a direction perpendicular to the heated pattern and which partially exposes the top edge surface of the sidewall portion the plurality of lower electrodes.

30. The method of claim 19, wherein the forming of the insulating layer comprises:

forming the insulating layer over the lower electrode; and

patterning the insulating layer to form the contact window, wherein the contact window is formed to a depth of 5 to 100 Å and

an aspect ratio of 0.0001 to 2.

31. The method of claim 19, wherein the forming of the heated pattern comprises:

forming a phase change layer on the insulating layer, the phase change layer contacting the partially exposed top edge surface of the sidewall portion of the lower electrode through the contact window; and

patterning the phase change layer to forming the heated pattern.

32. The method of claim 19, wherein the insulating layer is formed to a thickness of 20 to 200 Å

and is formed of a material having a resistivity of at least 10×

10<sup>−

3</sup> Ω

cm;

wherein the lower electrode is formed of at least one selected from the group consisting TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON, TaON, C, Ti, Ta, TiAl, Zr, Hf, Mo, Al, Al—

Cu, Al—

Cu—

Si, Cu, W, TiW, and WSix; and

wherein the heated pattern is formed of a material including at least one of Sb, Te, and Se.