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Low fabrication cost, fine pitch and high reliability solder bump

  • US 20080048320A1
  • Filed: 10/31/2007
  • Published: 02/28/2008
  • Est. Priority Date: 03/05/2001
  • Status: Active Grant
First Claim
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1. A chip comprising:

  • a silicon substrate;

    a dielectric layer over said silicon substrate;

    a pad over said dielectric layer;

    a topmost insulating layer of said chip over said dielectric layer, an opening in said topmost insulating layer exposing said pad, wherein said topmost insulating layer is polymer; and

    a bump on said pad and on a first top surface of said topmost insulating layer, wherein said bump comprises a metal layer on said pad, in said opening and on said topmost insulating layer and a copper pillar over said metal layer, wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar, and wherein said copper pillar has a second top surface higher than said first top surface.

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