Low fabrication cost, fine pitch and high reliability solder bump
First Claim
1. A chip comprising:
- a silicon substrate;
a dielectric layer over said silicon substrate;
a pad over said dielectric layer;
a topmost insulating layer of said chip over said dielectric layer, an opening in said topmost insulating layer exposing said pad, wherein said topmost insulating layer is polymer; and
a bump on said pad and on a first top surface of said topmost insulating layer, wherein said bump comprises a metal layer on said pad, in said opening and on said topmost insulating layer and a copper pillar over said metal layer, wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar, and wherein said copper pillar has a second top surface higher than said first top surface.
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Accused Products
Abstract
A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.
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Citations
20 Claims
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1. A chip comprising:
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a silicon substrate;
a dielectric layer over said silicon substrate;
a pad over said dielectric layer;
a topmost insulating layer of said chip over said dielectric layer, an opening in said topmost insulating layer exposing said pad, wherein said topmost insulating layer is polymer; and
a bump on said pad and on a first top surface of said topmost insulating layer, wherein said bump comprises a metal layer on said pad, in said opening and on said topmost insulating layer and a copper pillar over said metal layer, wherein said copper pillar has a height between 10 and 100 micrometers and greater than a transverse dimension of said copper pillar, and wherein said copper pillar has a second top surface higher than said first top surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A chip comprising:
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a silicon substrate;
a dielectric layer over said silicon substrate;
a pad over said dielectric layer;
a topmost insulating layer of said chip over said dielectric layer, an opening in said topmost insulating layer exposing said pad; and
a bump on said pad and on a first top surface of said topmost insulating layer, wherein said bump comprises a metal layer on said pad, in said opening and on said topmost insulating layer, a copper pillar over said metal layer and a solder material over said copper pillar, wherein said copper pillar has a height between 10 and 100 micrometers, and wherein said copper pillar has a second topmost surface higher than said first top surface. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification