LOW-POWER, LOW-JITTER, FRACTIONAL-N ALL-DIGITAL PHASE-LOCKED LOOP (PLL)
First Claim
1. A method for synthesizing frequencies with low-jitter using an all-digital fractional-N phase-locked loop (PLL) electronic circuit comprising a digital phase-frequency detector (DPFD) and a digital loop filer (DLF), said method comprising:
- receiving a reference signal and a feedback signal;
comparing a phase and frequency of the reference and feedback signals to determine a phase and frequency error between said reference and feedback signals;
generating a DPFD output comprising a multi-bit output;
filtering said DPFD output; and
generating a DLF output, wherein said DLF output is updated at each reference period.
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Abstract
A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.
50 Citations
23 Claims
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1. A method for synthesizing frequencies with low-jitter using an all-digital fractional-N phase-locked loop (PLL) electronic circuit comprising a digital phase-frequency detector (DPFD) and a digital loop filer (DLF), said method comprising:
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receiving a reference signal and a feedback signal; comparing a phase and frequency of the reference and feedback signals to determine a phase and frequency error between said reference and feedback signals; generating a DPFD output comprising a multi-bit output; filtering said DPFD output; and generating a DLF output, wherein said DLF output is updated at each reference period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, said electronic circuit comprising a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF),
wherein said DPFD adapted to: -
receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between said reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein said DLF is adapted to receive and filter said DPFD output and provide a DLF output, and wherein said DLF output is updated at each reference period. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, said electronic circuit comprising:
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a digital phase-frequency detector (DPFD) adapted to; receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between said reference and feedback signals; and provide a DPFD output comprising a multi-bit output; a digital loop filter (DLF) operatively connected to said DPFD and adapted to receive and filter said DPFD output and provide a DLF output, wherein said DLF output is updated at each reference period; and a digital-to-analog converter (DAC) operatively connected to said DLF and adapted to receive and convert said DLF output to an analog waveform, wherein said analog waveform comprises any of an analog voltage waveform and an analog current waveform, wherein said DAC comprises A most significant bits (MSBs) of data and B least significant bits (LSBs) of data, and wherein said DAC is adapted to provide an A+B bit conversion to said analog waveform. - View Dependent Claims (20, 21, 22, 23)
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Specification