Display system with single crystal Si thin film transistors

• US 20080049159A1
• Filed: 08/16/2007
• Published: 02/28/2008
• Est. Priority Date: 08/16/2006
• Status: Active Grant

• Current Assignee: Kopin Corporation
• Original Assignee: Kopin Corporation
• Inventors: Choi, Hong, Tsaur, Bor-Yeu, Lo, Jason
• Granted Patent: US 7,768,611 B2
• Time in Patent Office: Days
• US Class Current: 349/47
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A liquid crystal display comprises a display panel that includes at least one pixel transistor, at least one pixel electrode in electrical communication with the pixel transistor, at least one common electrode, and a liquid crystal material between the pixel electrode and the common electrode. The pixel transistor includes a thin film layer of essentially single crystal silicon that has a thickness in a range of between about 100 nm and about 200 nm. The pixel electrode has a thickness in a range of between about 5 nm and about 20 nm. The common electrode has a thickness of between about 50 nm and about 200 nm.

Claims

1. A liquid crystal display, comprising a display panel that includes:

a) at least one pixel transistor that includes a thin film layer of essentially single crystal silicon that has a thickness in a range of between about 100 nm and about 200 nm;

b) at least one pixel electrode in electrical communication with the pixel transistor and having a thickness in a range of between about 5 nm and about 20 nm;

c) at least one common electrode over the pixel electrode having a thickness of between about 50 nm and about 200 nm; and

d) a liquid crystal material between the pixel electrode and the common electrode.

2. The liquid crystal display of claim 1, further including a bonding layer between the transparent substrate and the pixel transistor.

3. The liquid crystal display of claim 1, wherein the thickness of the silicon thin film layer is in a range of between about 150 nm and about 200 nm.

4. The liquid crystal display of claim 3, wherein the thickness of the silicon thin film layer is about 200 nm.

5. The liquid crystal display of claim 1, wherein the pixel electrode includes polysilicon.

6. The liquid crystal display of claim 1, wherein the pixel electrode includes an indium tin oxide.

7. The liquid crystal display of claim 1, wherein the common electrode includes an indium tin oxide.

8. The liquid crystal display of claim 1, further including a first transparent substrate and a second transparent substrate, wherein the pixel transistor, the pixel electrode, the common electrode, and the liquid crystal material are between the first and the second transparent substrates.

9. The liquid crystal display of claim 8, wherein at least one of the first and the second transparent substrates includes at least one member chosen from glass, fused silica and sapphire.

10. The liquid crystal display of claim 1, wherein the pixel transistor is a metal-oxide thin film transistor that includes a drain, a source, a gate oxide layer over the silicon thin film layer, and a gate terminal over the gate oxide layer, wherein each of the drain and the source independently is in electrical contact with the silicon thin film layer.

11. The liquid crystal display of claim 10, wherein the gate oxide layer has a thickness in a range of between about 50 nm and about 150 nm.

12. The liquid crystal display of claim 11, wherein the gate oxide layer has a thickness in a range of between about 50 nm and about 100 nm.

13. The liquid crystal display of claim 10, wherein the gate oxide layer includes silicon dioxide.

14. The liquid crystal display of claim 10, wherein the gate terminal includes polysilicon.

15. The liquid crystal display of claim 10, wherein the pixel transistor further includes a spacer between at least one of the gate terminal and the source, and the gate terminal and the drain.

16. The liquid crystal display of claim 15, wherein the spacer has a width, measured from a gate terminal-spacer boundary, at the gate terminal, to the source, in a range of between about 300 nm and about 800 nm.

17. The liquid crystal display of claim 16, wherein the width is in a range of between about 500 nm and about 800 nm.

18. The liquid crystal display of claim 17, wherein the width is about 600 nm.

19. The liquid crystal display of claim 15, wherein the spacer has a width, measured from a gate terminal-spacer boundary, at the gate terminal, to the drain, in a range of between about 300 nm and about 800 nm.

20. The liquid crystal display of claim 19, wherein the width is in a range of between about 500 nm and about 800 nm.

21. The liquid crystal display of claim 20, wherein the width is about 600 nm.

22. The liquid crystal display of claim 1, further including an interconnect connecting the silicon thin film layer and the pixel electrode, wherein the Si thin film layer and the pixel electrode are in electrical communication with each other through the interconnect.

23. The liquid crystal display of claim 1, further including a control circuit for driving the display panel, which includes a shift register, clock driver and input level shifter.

24. The liquid crystal display of claim 23, wherein the control circuit includes at least one control transistor that includes a thin film layer of essentially single crystal silicon, the silicon thin film layer having a thickness in a range of between about 100 mu and about 200 nm.

25. The liquid crystal display of claim 24, wherein the control transistor is included in at least one of the shift register, clock driver and input level shifter.