SCALABLE MEMORY SYSTEM

• US 20080049505A1
• Filed: 08/22/2007
• Published: 02/28/2008
• Est. Priority Date: 08/22/2006
• Status: Active Grant

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: PRZYBYLSKI, Steven, OH, HakJune, PYEON, Hong Beom, KIM, Jin-Ki
• Granted Patent: US 8,407,395 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

Claims

1. A memory system comprising:

a controller having a serial channel output port for providing a serial bitstream command packet, and a serial channel input port for receiving a serial bitstream read data packet, the serial bitstream command packet including an operational code and a device address; and

,

a memory device having an input port for receiving the serial bitstream command packet from the controller and for executing the operation code if the device address corresponds to the memory device, the memory device providing the serial bitstream command packet through an output port and subsequently providing the serial bitstream read data packet through the output port if the operation code corresponds to a read function.

2. The memory system of claim 1, further including at least one intervening memory device coupled in series between the memory device and the controller, the at least one intervening memory device having an input port for receiving and passing the serial bitstream command packet to the memory device, and subsequently providing the serial bitstream read data packet if the device address corresponds to the memory device and the operation code corresponds to a read function.

3. The memory system of claim 2, wherein complementary clock signals are provided to the memory device and the at least one intervening memory device in parallel.

4. The memory system of claim 2, wherein complementary clock signals are provided to the at least one intervening memory device, and passed by the at least one intervening memory device to the memory device, and passed by the memory device to the controller.

5. The memory system of claim 2, further including an expansion link between the controller and the memory device for receiving one of an expansion module and a jumper.

6. The memory system of claim 5, wherein the at least one intervening memory device is part of an expansion module having coupling means configured for electrical coupling with the expansion link.

7. The memory system of claim 2, wherein the memory device and the at least one intervening memory device each include a native memory core and a serial interface and control logic block for controlling the native memory core in response to the serial bitstream command packet.

8. The memory system of claim 7, wherein the memory device native memory core and the at least one intervening memory device native memory core are NAND flash based.

9. The memory system of claim 7, wherein the memory device native memory core and the at least one intervening memory device native memory core are different.

10. The memory system of claim 2, wherein the native memory core includes one of DRAM, SRAM, NAND flash and NOR flash memory cores.

11. The memory system of claim 1, wherein the serial bitstream command packet has a modular structure where the size of the serial bitstream command packet is variable.

12. The memory system of claim 11, wherein the serial bitstream command packet includes a command field for providing the operation code and the device address.

13. The memory system of claim 12, wherein the command field includes a first sub-field for providing the operation code, and a second sub-field for providing the device address.

14. The memory system of claim 11, wherein the serial bitstream command packet includes a command field for providing the operation code and the device address, and an address field for providing one of a row address and a column address.

15. The memory system of claim 11, wherein the serial bitstream command packet includes a command field for providing the operation code and the device address, an address field for providing one of a row address and a column address, and a data field for providing write data.

16. The memory system of claim 11, wherein the controller provides a command strobe in parallel with the serial bitstream command packet, the command strobe having an active level matching the length of the serial bitstream command packet.

17. The memory system of claim 16, wherein the controller provides a data input strobe in parallel with the serial bitstream read data packet, the data input strobe having an active level matching the length of the serial bitstream read data packet.

18. The memory system of claim 17, wherein the memory device latches the serial bitstream command packet in response to the active level of the command strobe when the device address corresponds to the memory device.

19. The memory system of claim 18, wherein the memory device output port is enabled in response to the active level of the data input strobe.

20. The memory system of claim 19, wherein the command strobe and the data input strobe are non-overlapping signals.

21. The memory system of claim 19, wherein the command strobe and the data input strobe are separated by at least one data latching clock edge.

22. The memory system of claim 19, wherein the command strobe is separated from an adjacent command strobe by at least one data latching clock edge.

23. The memory system of claim 19, wherein the data input strobe is separated from an adjacent data input strobe by at least one data latching clock edge.

24. A command packet includes a series of bits for a memory system having serially connected memory devices, comprising:

a command field for selecting a memory device of the serially connected memory devices to execute a specific memory operation.

25. The command packet of claim 24, wherein the command field includes a first sub-field for providing a device address for selecting the memory device, and a second sub-field for providing an operation code corresponding to the specific memory operation.

26. The command packet of claim 25, wherein the command packet further includes an address field following the command field for providing one of a row address and a column address when the operation code corresponds to a read or write operation, the address field having a bit length corresponding to the row address or the column address.

27. The command packet of claim 26, wherein the command packet further includes a data field following the address field for providing write data for storage in the memory device when the operation code corresponds to the write operation, the data field having a bit length corresponding to the write data.

28. A method for executing concurrent operations in a selected memory device of a memory system having serially connected memory devices, comprising:

receiving a first command;

executing core operations in a first memory bank of the selected memory device in response to the first command;

receiving a second command during execution of core operations in the first memory bank; and

,

executing core operations in a second memory bank of the selected memory device in response to the second command.

29. The method of claim 28, further including

receiving a third command for requesting result information from one of the first memory bank and the second memory bank, and

outputting a read data packet containing the result information in response to the third command.

30. The method of claim 29, wherein the result information includes one of status register data and read data.

31. The method of claim 29, wherein the first command, the second command and the third command are command packets including a series of bits logically configured to include

a mandatory command field for providing an operation code and a device address,

an optional address field following the command field for providing one of a row and column address when the operation code corresponds to a read or write operation, and,

an optional data field following the address field for providing write data when the operation code corresponds to the write operation.

32. The method of claim 31, wherein

a first command strobe is received in parallel with the first command, the first command strobe having an active duration corresponding to the length of the first command, and

a second command strobe is received in parallel with the second command, the second command strobe having an active duration corresponding to the length of the second command.

33. The method of claim 32, wherein a data input strobe is received for enabling outputting of the read data packet while the data input strobe is at the active level.

34. The method of claim 33, wherein the first command strobe and the second command strobe are separated by at least one data latching clock edge.

35. The method of claim 33, wherein the second command strobe and data input strobe are separated by at least one data latching clock edge.

36. The method of claim 28, further including powering up the selected memory device before receiving the first command.

37. The method of claim 36, wherein the step of powering up includes

asserting a control signal to maintain the selected memory device in a default state prior to a power transition;

transitioning a power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted;

waiting for a predetermined duration of time to allow the power level to stabilize; and

,

de-asserting the control signal to release the selected memory device from the default state thereby preventing accidental program or erase operation in the selected memory device.

38. The method of claim 37, wherein the second voltage level is a minimum voltage level for stable circuit operation.

39. The method of claim 37, wherein the second voltage level is a maximum operating voltage level of a power supply.

40. The method of claim 37, wherein the first voltage level corresponds to a low power mode operating voltage level of a power supply.

41. The method of claim 37, wherein the first voltage level corresponds to the absence of a power supply.

42. The method of claim 37, wherein maintaining the memory device in the default state comprises setting device registers in the memory device to a default value.

43. The method of claim 42, wherein the device registers include command registers.

44. The method of claim 37, further comprising the step of performing device initialization upon release of the memory device from the default state.

45. The method of claim 44, wherein the step of performing device initialization comprises generating device address and device identifier information for the memory device.

46. The method of claim 36, wherein the step of powering up includes

asserting a control signal at a first time, to maintain the memory device in a default state prior to a power transition;

transistioning a power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted;

waiting for a predetermined duration of time to allow the power level to stabilize; and

,

de-asserting the control signal at a third subsequent time for releasing the memory device from the default state thereby preventing accidental program or erase operation in the memory device.

47. A memory system comprising a plurality of memory devices and a controller for controlling the devices,

the controller having an output port for providing a bitstream command packet to a first device of the plurality of memory devices, the bitstream command packet including an operational code and a device address,

each of the plurality of memory devices receiving the bitstream command packet from one of the controller and a prior memory device and executing the operation code if the device address corresponds thereto, each of the plurality of memory devices providing the bitstream command packet to one of a next memory device and the controller, a bitstream read data packet being provided from a last memory device of the plurality of memory devices to the controller if the operation code corresponds to a read function.

48. The memory system of claim 47, wherein the plurality of memory devices is connected in series, the first and last memory devices being connected to the controller.

49. The memory system of claim 47, wherein the controller sends a bitstream data packet to the first device of the plurality of memory devices.

50. The memory system of claim 49, wherein the bitstream data packet from the controller and the bitstream read data packet comprises a serial bitstream.

51. The memory system of claim 49, wherein the bitstream data packet from the controller and the bitstream read data packet comprises parallel bitstreams.

52. The memory system of claim 47, wherein the plurality of memory devices are of the same type or a mix of different types of memory devices.

53. A memory system comprising a plurality of memory devices and a controller for controlling the devices, the memory system being capable of performing the function of powering up a selected memory device before receiving a first command.

54. The memory system of claim 53, wherein the function of powering up comprises:

asserting a control signal to maintain the selected memory device in a default state prior to a power transition;

transitioning a power level of the selected memory device from a first voltage level to a second voltage level while the control signal is asserted;

waiting for a predetermined duration of time to allow the power level to stabilize; and

,

de-asserting the control signal to release the selected memory device from the default state thereby preventing accidental program or erase operation in the selected memory device.

55. The memory system of claim 53, wherein the function of powering up comprises:

asserting a control signal at a first time, to maintain the memory device in a default state prior to a power transition;

transistioning a power level of the memory device from a first level to a second level at a second subsequent time while the control signal is asserted;

waiting for a predetermined duration of time to allow the power level to stabilize; and

,

de-asserting the control signal at a third subsequent time for releasing the memory device from the default state thereby preventing accidental program or erase operation in the memory device.