SCALABLE MEMORY SYSTEM
First Claim
1. A memory system comprising:
- a controller having a serial channel output port for providing a serial bitstream command packet, and a serial channel input port for receiving a serial bitstream read data packet, the serial bitstream command packet including an operational code and a device address; and
, a memory device having an input port for receiving the serial bitstream command packet from the controller and for executing the operation code if the device address corresponds to the memory device, the memory device providing the serial bitstream command packet through an output port and subsequently providing the serial bitstream read data packet through the output port if the operation code corresponds to a read function.
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Accused Products
Abstract
A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
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Citations
55 Claims
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1. A memory system comprising:
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a controller having a serial channel output port for providing a serial bitstream command packet, and a serial channel input port for receiving a serial bitstream read data packet, the serial bitstream command packet including an operational code and a device address; and
,a memory device having an input port for receiving the serial bitstream command packet from the controller and for executing the operation code if the device address corresponds to the memory device, the memory device providing the serial bitstream command packet through an output port and subsequently providing the serial bitstream read data packet through the output port if the operation code corresponds to a read function. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A command packet includes a series of bits for a memory system having serially connected memory devices, comprising:
a command field for selecting a memory device of the serially connected memory devices to execute a specific memory operation. - View Dependent Claims (25, 26, 27)
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28. A method for executing concurrent operations in a selected memory device of a memory system having serially connected memory devices, comprising:
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receiving a first command;
executing core operations in a first memory bank of the selected memory device in response to the first command;
receiving a second command during execution of core operations in the first memory bank; and
,executing core operations in a second memory bank of the selected memory device in response to the second command. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. A memory system comprising a plurality of memory devices and a controller for controlling the devices,
the controller having an output port for providing a bitstream command packet to a first device of the plurality of memory devices, the bitstream command packet including an operational code and a device address, each of the plurality of memory devices receiving the bitstream command packet from one of the controller and a prior memory device and executing the operation code if the device address corresponds thereto, each of the plurality of memory devices providing the bitstream command packet to one of a next memory device and the controller, a bitstream read data packet being provided from a last memory device of the plurality of memory devices to the controller if the operation code corresponds to a read function.
- 53. A memory system comprising a plurality of memory devices and a controller for controlling the devices, the memory system being capable of performing the function of powering up a selected memory device before receiving a first command.
Specification