Graphics Accelerator
First Claim
1. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:
- a decoder operable to decode a signal having N states, where N is an integer greater than one, and operable to generate tentative decisions regarding a path and a final decision;
a single-state decision feedback equalizer operable to receive the tentative decisions and to produce a single-state intersymbol interference (ISI) compensation signal corresponding to an ISI component based on the tentative decisions; and
a state multiplication circuit adapted to produce an N-state representation signal, suitable for decoding by the decoder, based on the single-state ISI compensation signal.
3 Assignments
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Accused Products
Abstract
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
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Citations
27 Claims
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1. An integrated circuit communication device configured for operation over a multi-pair transmission channel, the communication device comprising:
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a decoder operable to decode a signal having N states, where N is an integer greater than one, and operable to generate tentative decisions regarding a path and a final decision;
a single-state decision feedback equalizer operable to receive the tentative decisions and to produce a single-state intersymbol interference (ISI) compensation signal corresponding to an ISI component based on the tentative decisions; and
a state multiplication circuit adapted to produce an N-state representation signal, suitable for decoding by the decoder, based on the single-state ISI compensation signal. - View Dependent Claims (3, 8)
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2. (canceled)
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4-7. -7. (canceled)
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9. A method of processing a communication signal having N states and transmitted over a multi-pair transmission channel, where N is an integer greater than one, the method comprising steps of:
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(a) generating tentative decisions regarding a path and a final decision;
(b) producing a single-state intersymbol interference (ISI) compensation signal corresponding to an ISI component based on the tentative decisions;
(c) producing an N-state representation signal based on the single-state ISI compensation signal; and
(d) decoding the N-State representation signal. - View Dependent Claims (11)
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10. (canceled)
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12-15. -15. (canceled)
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16. An integrated circuit communication device, the communication device comprising:
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a decoder operable to decode a signal having a plurality of states, and generating tentative decisions regarding a path and a final decision;
a single-state decision feedback equalizer operable to receive the tentative decisions and to produce a single-state intersymbol interference (ISI) compensation signal corresponding to a first ISI component based on the tentative decisions; and
a state multiplication circuit operable to receive a tail component generated by subtracting the single-state ISI compensation signal from a signal sample and to produce a signal having a plurality states, suitable for decoding by the decoder, based on the tail component. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A method of processing a communication signal having a plurality of states, the method comprising steps of:
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(a) generating tentative decisions regarding a path and a final decision;
(b) producing a single-state intersymbol interference (ISI) compensation signal corresponding to a first ISI component based on the tentative decisions;
(c) subtracting the single-state ISI compensation signal from a signal sample to produce a tail component;
(d) producing a representation signal having a plurality of states based on the tail component; and
(e) decoding the representation signal. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification