RFID decoding subsystem with decode module

• US 20080049870A1
• Filed: 07/20/2006
• Published: 02/28/2008
• Est. Priority Date: 07/20/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza), Shoarinejad, Kambiz
• Granted Patent: US 7,991,080 B2
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: H04L 27/1525 using quadrature demodulation
• CPC Class Codes: H04L 27/1566 using synchronous sampling

Abstract

A radio frequency identification (RFID) decoding subsystem includes a pre-decode module and a decode module. The pre-decode module is coupled to process down-converted RFID signals into pre-decoded baseband data. The decode module is coupled to: enable a counting process based on the pre-decoded baseband data to produce a count resultant; and compare the count resultant with a threshold at a data bit interval to produce decoded RFID data.

Claims

1. A radio frequency identification (RFID) decoding subsystem comprises:

pre-decode module coupled to process down-converted RFID signals into pre-decoded baseband data; and

decode module coupled to;

enable a counting process based on the pre-decoded baseband data to produce a count resultant; and

compare the count resultant with a threshold at a data bit interval to produce decoded RFID data.

2. The RFID decoding subsystem of claim 1, wherein the pre-decoded baseband data comprises at least one of:

amplitude estimation of the down-converted RFID signals; and

limited in-phase component signals or limited quadrature component signals selected based on received signal strength of in-phase component and quadrature component of the down-converted RFID signals.

3. The RFID decoding subsystem of claim 1, wherein the decode module comprises:

a clock source coupled to generate a clock signal having a rate greater than an inverse of the data bit interval;

a first counter enabled based on a first state of the pre-decoded baseband signal to count cycles of the clock signal during at least one period of the data bit interval to produce a first count;

a second counter enabled based on a second state of the pre-decoded baseband signal to count cycles of the clock signal during at least one period of the data bit interval to produce a second count; and

decision module coupled to produce the decoded RFID data based on the first and second counts.

4. The RFID decoding subsystem of claim 3, wherein the decision module functions to:

compare at least one of the first and second counts with at least one threshold;

when the at least one of the first and second counts compare unfavorably with the at least one threshold, decode the pre-decoded baseband signal for the at least one period of the data bit interval as a first decoded value; and

when the at least one of the first and second counts compares favorably with the at least one threshold, decode the pre-decoded baseband signal for the at least one period of the data bit interval as a second decoded value.

5. The RFID decoding subsystem of claim 1, wherein the decode module functions to:

determine whether a decoding error exists for the RFID data over a plurality of data bit intervals;

when the decoding error exists, enable the counting process based on complimentary pre-decoded baseband data to produce a complimentary count resultant; and

compare the complimentary count resultant with the threshold at the data bit interval to produce decoded RFID data.

6. A radio frequency identification (RFID) decoding subsystem comprises:

pre-decode module coupled to process down-converted RFID signals into pre-decoded baseband data; and

decode module coupled to;

sample the pre-decoded baseband data at a rate greater than a data rate to produce at least a first decision metric and a second decision metric per data bit interval;

compare the first and second decision metrics;

when the first and second decision metrics substantially match, produce a first decoded value; and

when the first and second decision metrics do not substantially match, produce a second decoded value.

7. The RFID decoding subsystem of claim 6, wherein the decode module comprises:

a first sampling module coupled to produce the first decision metric during a first portion of the data bit interval;

a second sampling module coupled to produce the second decision metric during a second portion of the data bit interval; and

comparison module coupled to compare at least one of sign and magnitude of the first and second decision metrics to produce the first or second decoded value.

8. The RFID decoding subsystem of claim 7, wherein each of the first and second sampling modules comprises:

a clock source coupled to produce a clock signal having a rate greater than an inverse of the data bit interval;

a first counter coupled to count a first state of the pre-decoded baseband data during the first or second portion of the data bit interval to produce a first count, wherein the first counter is clocked by the clock signal;

a second counter coupled to count a second state of the pre-decoded baseband data during the first or second portion of the data bit interval to produce a second count, wherein the second counter is clocked by the clock signal; and

output module coupled to;

compare the first count with the second count;

output the first state as the first or second decision metric when the first count compared favorably to the second count; and

output the second state as the first or second decision metric when the first count compared unfavorably to the second count.

9. The RFID decoding subsystem of claim 6, wherein the pre-decoded baseband data comprises:

limited in-phase signals;

limited quadrature signals; and

a representation of signal strength of the pre-decoded baseband data.

10. The RFID decoding subsystem of claim 9, wherein the decode module comprises:

an in-phase decode module coupled to;

sample the limited in-phase signals at the rate greater than the data rate to produce at least a first in-phase decision metric and a second in-phase decision metric per data bit interval;

compare the first and second in-phase decision metric;

when the first and second in-phase decision metrics substantially match, produce a first in-phase decoded value; and

when the first and second in-phase decision metrics do not substantially match, produce a second in-phase decoded value;

a quadrature decode module coupled to;

sample the limited quadrature signals at the rate greater than the data rate to produce at least a first quadrature decision metric and a second quadrature decision metric per data bit interval;

compare the first and second quadrature decision metrics;

when the first and second quadrature decision metrics substantially match, produce a first quadrature decoded value; and

when the first and second quadrature decision metrics do not substantially match, produce a second quadrature decoded value;

a selection module operably coupled to provide the first or second in-phase decoded value as the first or second decoded value when the representation of signal strength of the pre-decoded baseband data is in an in-phase state and provide the first or second quadrature decoded value as the first or second decoded value when the representation of signal strength of the pre-decoded baseband data is in a quadrature state.

11. A radio frequency identification (RFID) decoding subsystem comprises:

pre-decode module coupled to process down-converted RFID signals into limited in-phase component signals and limited quadrature component signals; and

decode module coupled to;

mix the limited in-phase component signals with a reference oscillation to produce mixed in-phase component signals;

mix the limited quadrature component signals with a quadrature reference oscillation to produce mixed quadrature component signals; and

process the mixed in-phase component signals and the mixed quadrature component signals to produce decoded RFID data, wherein the reference oscillation and the quadrature reference oscillation are based on rate of encoded RFID data.

12. The RFID decoding subsystem of claim 11, the decode module process the mixed in-phase component signals and the mixed quadrature component signals by:

sampling one of the mixed in-phase component signals and the mixed quadrature component signals by another one of the mixed in-phase component signals and the mixed quadrature component signals to produce the decoded RFID data.

13. The RFID decoding subsystem of claim 12, wherein the decode module comprises:

a D flip-flop having a D input, a clock input, and an output, wherein the D input is coupled to receive the mixed in-phase component signals and the clock input is coupled to receive the mixed quadrature component signals, and wherein the output provides the decoded RFID data.

14. The RFID decoding subsystem of claim 11 comprises:

a first rate of oscillation to represent a first state of the down-converted RFID signals;

a second rate of oscillation to present a second state of the down-converted RFID signals; and

the reference oscillation having a rate based on the a function of the first and second rates.