DUAL STRESS LINER DEVICE AND METHOD

• US 20080050869A1
• Filed: 07/05/2006
• Published: 02/28/2008
• Est. Priority Date: 07/05/2006
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Inventors: SUDO, Gaku
• Granted Patent: US 7,585,720 B2
• Time in Patent Office: Days
• US Class Current: 438/228
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

depositing a first stress liner on a silicon layer, said first stress liner applying a first type of stress on the silicon layer;

depositing a second stress liner on the silicon layer, wherein a portion of said second stress liner overlaps a portion of said first stress liner, said second stress liner applying a second type of stress, opposite the first type of stress, on the silicon layer;

removing said portion of said second stress liner overlapping said portion of said first stress liner; and

forming first and second conductive contacts through said first and second stress liners, respectively.

2. The method of claim 1, wherein said first and second stress liners overlap over a conductive interconnect structure on said semiconductor device.

3. The method of claim 2, further comprising the step of embedding an oxide layer in the silicon layer under said conductive interconnect structure.

4. The method of claim 2, further comprising the step of forming a third contact through the first and second stress liners to electrically contact said conductive interconnect structure.

5. The method of claim 1, further comprising the step of depositing an insulating film over said first and second stress liners before said step of removing.

6. The method of claim 5, further comprising the step of depositing a second insulating film over said first insulating film after said step of removing and before said step of forming said first and second contacts.

7. The method of claim 1, wherein said first stress liner is a tensile stress liner and said second stress liner is a compressive stress liner.

8. The method of claim 7, wherein said stress liners are SiN stress liners.

9. A semiconductor device, comprising:

a substrate;

first and second field-effect transistors formed on and in said substrate;

a tensile stress liner formed over the first field-effect transistor;

a compression stress liner formed over the second field-effect transistor; and

a conductive contact disposed between the first and second field-effect transistors, wherein a first side of said contact is adjacent to said tensile stress liner, an opposite second side of said contact is adjacent to said compression stress liner, and wherein said stress liners do not overlap.

10. The device of claim 9, wherein said stress liners are SiN stress liners.

11. The device of claim 9, further comprising a first insulating layer having a top surface at a height common with a top surface of one of said stress liners.

12. The device of claim 11, further comprising a second insulating layer formed on said first insulating layer.

13. The device of claim 12, wherein said contact is formed in a trench formed in said second insulating layer but not in said first insulating layer.

14. The device of claim 13, further comprising a second contact extending through both of said insulating layers and only one of said stress layers to reach one of said field-effect transistors.

15. The device of claim 9, wherein said contact is an interconnect contact that reaches an interconnect gate structure, and where said interconnect gate structure is above an isolation region of said substrate.

16. A method of manufacturing a semiconductor device, comprising the steps of:

forming first and second pluralities of transistor wells on a semiconductor substrate;

depositing a first stress liner contacting said first plurality of said wells;

depositing a second stress liner contacting said second plurality of said wells, wherein a portion of said second stress liner overlaps a portion of said first stress liner, wherein one of said stress liners is a tensile stress liner, and the other of said stress liners is a compression stress liner;

depositing a first insulating film on said stress liners;

polishing said first insulating film and said second stress liner to remove said portion of said second stress liner, wherein said polishing uses said first stress liner and a portion of the second stress liner as a stopper;

depositing a second insulating film on said first insulating film after said polishing;

forming first and second contacts through said first and second stress liners, respectively.

17. The method of claim 16, wherein said step of forming first and second contacts further comprises the step of forming a trench through both of said insulating films and only one of said stress liners to reach first and second ones of said wells, respectively.

18. The method of claim 16, further comprising the step of forming a third contact through at least said second insulating film to reach a gate structure on said device, wherein said contact contacts said first stress liner on a first side, and said second stress liner on a second side.

19. The method of claim 18, wherein said contact directly contacts said first and second stress liners.

20. The method of claim 18, wherein said gate structure separates said semiconductor into n-type and p-type device regions.