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Top layers of metal for high performance IC's

  • US 20080050909A1
  • Filed: 10/31/2007
  • Published: 02/28/2008
  • Est. Priority Date: 12/21/1998
  • Status: Active Grant
First Claim
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1. A method for fabricating a chip, comprising:

  • providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure and over said first and second dielectric layers, a first passivation opening in said passivation layer exposing a first pad of said first metallization structure, wherein said first passivation opening has a transverse dimension between 0.1 and 50 micrometers, and a second passivation opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other;

    forming a first polymer layer over said passivation layer, a first polymer opening in said first polymer layer exposing said first pad, and a second polymer opening in said first polymer layer exposing said second pad, wherein said first polymer layer has a thickness of between 2 and 50 micrometers and greater than those of said passivation layer and said first and second dielectric layers; and

    forming a second metallization structure over said first polymer layer and over said first and second pads, wherein said first pad is connected to said second pad through, said first passivation opening, said first polymer opening, said second metallization, said second polymer opening and said second passivation opening, wherein said forming said second metallization structure comprising sputtering a adhesion layer over said first polymer layer and said first and second pads, wherein said adhesion layer has a thickness between 0.01 and 3 micrometers, sputtering a seed layer over said adhesion layer, wherein said seed layer has a thickness between 0.05 and 3 micrometers, forming a photoresist layer on said seed layer,wherein an opening in said photoresist layer exposes said seed layer, wherein said photoresist layer has a thickness between 2 and 100 micrometers, electroplating a first copper layer on said seed layer in said opening in said photoresist layer, wherein said first copper layer has a thickness between 2 and 100 micrometers, removing said photoresist layer, removing said seed layer and said adhesion layer using said first copper layer as an etch mask.

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