Galvanic isolation integrated in a signal channel

• US 20080051158A1
• Filed: 08/22/2006
• Published: 02/28/2008
• Est. Priority Date: 08/22/2006
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hemmah, Steven, Male, Barry Jon
• Application Number:
  US11/507,999
• Publication Number:
  US 20080051158A1
• Time in Patent Office: Days
• US Class Current: 455/572
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

A communication link between two isolated electrical devices provides for adjustable impedances coupled to the communication link signal paths to balance the signal paths and improve CMRR. The communication link may be a bidirectional capacitively coupled differential signal line to improve noise rejection. The capacitance may be realized as portions of circuit board traces, lead frames, IC pins and/or molding on ICs or on an IC package. The variable impedance compensates for variances in the capacitive coupling values so that the signal paths react similarly in the presence of noise or interference. The variable impedance may be set or programmed from stored values that may be digital or analog. The capacitive coupling of the differential signal line permits integration of isolated devices in a common package.

Claims

1. A system for transferring signals between an electrical circuit with a first common reference and an electrical circuit with a second common reference, the system comprising:

a capacitively coupled signal line coupled between the first and second referenced electrical circuits to permit transfer of signals and high-voltage isolation between the first and second referenced electrical circuits;

a transmitter or receiver in the first referenced electrical circuit and coupled to the signal line to send or receive a signal, respectively;

a receiver or transmitter in the second referenced electrical circuit and coupled to the signal line to receive or send a signal, respectively, in conjunction with the transmitter or receiver of the first referenced electrical circuit; and

an impedance coupled to the signal line and operable to be configured to compensate capacitive values in the capacitively coupled signal line.

2. The system according to claim 1, wherein the impedance further comprises a variable impedance.

3. The system according to claim 1, wherein the impedance further comprises a programmable impedance.

4. The system according to claim 1, further comprising a parameter storage device for storing a parameter to influence a value of the impedance.

5. The system according to claim 4, wherein the impedance further comprises a programmable impedance, the parameter storage device providing a parameter value to contribute to programming a value of the impedance.

22. The system according to claim 1, wherein the system is encapsulated in an integrated circuit (IC) package.

6. A bi-directional communication link between electrically isolated devices, comprising:

bi-directional transceivers coupled to each end of the communication link;

a capacitive value associated with each signal path in the bi-directional communication link;

one or more compensation impedances coupled to one or more signal paths of the bi-directional communication link; and

the one or more compensation impedances having a value to compensate for mismatches in the capacitive values to obtain balanced signal paths in the bi-directional communication link.

7. The communication link according to claim 6, further comprising a value of the one or more impedances being set to optimize a Common Mode Rejection Ratio (CMRR) of the bi-directional communication link.

8. The communication link according to claim 6, further comprising a capacitive coupling between the transceivers to realize the bi-directional communication link, the capacitive coupling providing a high-voltage isolation between the electrically isolated devices.

9. The communication link according to claim 8, wherein the capacitance for the capacitive coupling is formed with circuit board traces coupled to the electrically isolated devices.

10. The communication link according to claim 8, wherein the capacitance for the capacitive coupling is formed with lead frames associated with the electrically isolated devices.

11. The communication link according to claim 8, wherein the capacitance for the capacitive coupling is formed with a molding compound at least partially covering the communication link.

12. The communication link according to claim 8, wherein the capacitance for the capacitive coupling is formed with discrete capacitors.

13. The communication link according to claim 6, further comprising a parameter storage device for holding parameter values that can influence the compensation impedances to obtain the balanced signal paths.

14. The communication link according to claim 13, wherein the storage device is digital.

15. The communication link according to claim 13, wherein the storage device is analog.

23. The communication link according to claim 6, wherein the communication link and electrically isolated devices are contained within an IC package.

16. A method for communicating a signal across a high-voltage isolation barrier, comprising:

providing a capacitively coupled communication link between the two electrically isolated devices;

compensating one or more capacitive values in the capacitively coupled communication link;

tuning the compensation to optimize CMRR.

17. The method according to claim 16, wherein tuning further comprises:

developing a voltage across the capacitively coupled communication link; and

adjusting an impedance coupled to the capacitively coupled communication link to nullify voltage mismatches.

18. The method according to claim 17, further comprising implementing tuning one time to adjust the impedance.

19. The method according to claim 17, further comprising implementing tuning at predetermined intervals or upon predetermined events.

20. The method according to claim 17, further comprising implementing tuning on a continuous basis.

21. The method according to claim 16, further comprising storing a parameter value related to tuning to contribute to compensating the one or more capacitive values at a later time.