FLASH MEMORY INTERFACE DEVICE

• US 20080052448A1
• Filed: 07/19/2007
• Published: 02/28/2008
• Est. Priority Date: 07/20/2006
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Minz, Deboleena, Varshney, Sanjeev
• Granted Patent: US 8,140,738 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory

Abstract

A memory interface module provides interfacing between a host processor with multiple flash memories and parallel interfaces of varying protocols. The interface module includes multiple register files, multiple operation information registers, an internal memory, a flash interface portion, and a finite state machine (FSM). The register files receive a command from the host processor for controlling an operation of multiple flash memories. The operation information registers execute and store the command and operation information. The internal memory receives and stores host data from the host processor. The internal memory further stores flash data extracted from multiple flash memories. The flash interface portion interacts with the memory devices connected to the controller. The FSM extracts the command and the operation information from the register files, which are programmed by the user and controls the control signals of the memory devices connected to the controller through the flash interface.

Claims

1. A memory interface module interfacing between a host processor and a plurality of flash memories, the plurality of flash memories obeying a plurality of protocols, said memory interface module comprising:

a plurality of register files receiving a command from the host processor to control an operation of the plurality of flash memories and a plurality of parallel interfaces;

a plurality of operation information registers for executing and storing the command and an operation information;

an internal memory receiving and storing host data from the host processor and storing flash data extracted from the plurality of flash memories to transmit to the host processor;

a flash interface portion performing a plurality of tasks, said tasks comprising;

controlling a control signal to operate the plurality of flash memories;

outputting one or more of the command, the operation information, and the host data; and

controlling a data bus for enabling data transfer to the plurality of flash memories; and

a finite state machine (FSM) extracting the command and the operation information and controlling the internal memory and the flash interface portion to execute the command,

said memory interface module provides a flexibility to control the control signal through a plurality of pre-defined states, and

said finite state machine (FSM) generating the control signal, such that the plurality of pre-defined states and their transitions being controlled by an user.

2. The memory interface module as claimed in claim 1, wherein the plurality of flash memories is selected from a group consisting of flash memories, SDRAMs, and parallel interfaces.

3. The memory interface module as claimed in claim 1, wherein the operation information comprises a starting address to be assigned to a location of said flash memory in which an operation according to the command is performed.

4. The memory interface module as claimed in claim 1, wherein the internal memory comprises:

a booting memory for storing a booting code to boot a system;

one of a buffer, and a register file for storing the host data and the flash data; and

an ECC checker.

5. The memory interface module as claimed in claim 1, wherein the plurality of register files comprises:

an address register for storing an address of a memory read/write location;

a command register for storing device commands for a particular memory being interfaced; and

a timing register for storing one or more of a setup time information, a hold time information, and a memory device timing information.

6. The memory interface module as claimed in claim 5, wherein the plurality of register files further comprising a status register for storing an operation status information of the command, and an execution result of the command.

7. A method of interfacing between a host processor and a plurality of flash memories through a memory interface module, the plurality of flash memories obeying a plurality of protocols, said method comprising:

receiving a command from the host processor to control an operation of the plurality of flash memories through a plurality of register files;

executing and storing the command and an operation information through an operation information register;

decoding the command and the operation information through a flash interface portion; and

executing an operation according to the decoded command, said memory interface module provides a flexibility to control the control signal through a plurality of pre-defined states, wherein the plurality of pre-defined states and their transitions are controlled by a user.

8. An interface between a host processor and a plurality of different types of flash memory, comprising:

a plurality of input/output pins connected through a glue logic to the plurality of different types of flash memory; and

a finite state machine having a plurality of states, the identification of the states and the transition among and between those states being specified by a user of the interface;

the finite state machine transitioning between the states to control the operation of the plurality of input/output pins so as to interface with the plurality of different types of flash memory for data exchange.

9. The interface of claim 8 wherein transition among and between the states of the finite state machine is controlled through execution of software comprising a plurality of instruction-operand pairs, certain ones of the instruction-operand pairs controlling the generation of one or more signals at the plurality of input/output pins for interfacing with a certain one of the plurality of different types of flash memory.

10. The interface of claim 9 wherein the finite state machine executes sequences of the instruction-operand pairs in controlling operation of the plurality of input/output pins.

11. The interface of claim 8 wherein the plurality of input/output pins includes a first input/output pin connected through the glue logic to both a first type flash memory and a second type flash memory, the finite state machine controlling the first input/output pin to operate in a first mode for interfacing with first type flash memory and a second mode for interfacing with second type flash memory.

12. The interface of claim 11 wherein the plurality of memories comprise a first type flash memory and a second type flash memory, and wherein the first type flash memory utilizes a first protocol and the second type flash memory utilizes a second protocol, the finite state machine controlling the first input/output pin to operate in accordance with the first protocol for interfacing with first type flash memory and in accordance with the second protocol for interfacing with second type flash memory.

13. The interface of claim 8 wherein the plurality of memories comprise a first type flash memory and a second type flash memory, and wherein the first type flash memory utilizes a first control signal sequence and the second type flash memory utilizes a second control signal sequence, the finite state machine controlling the input/output pins to effectuate the first control signal sequence for interfacing with first type flash memory and the second control signal sequence for interfacing with second type flash memory.

14. The interface of claim 8 wherein the plurality of memories comprise a first type flash memory and a second type flash memory, and wherein the first type flash memory is controlled in accordance with a first protocol and the second type flash memory is controlled in accordance with a second protocol, the finite state machine controlling the input/output pins in accordance with the first protocol for interfacing with first type flash memory and in accordance with the second protocol for interfacing with second type flash memory.

15. The interface of claim 8 wherein the plurality of memories comprise a first type flash memory and a second type flash memory, and wherein the first type flash memory is controlled by a first combination and sequencing of states in the finite state machine and the second type flash memory is controlled in accordance with a second combination and sequencing of states in the finite state machine, the finite state machine responding to a host processor request for access to one of the first and second types of flash memory by executing the corresponding combination and sequencing of states so as to control the input/output pins to interface with the requested flash memory.

16. The interface of claim 8 wherein the finite state machine transitions between the states to control generation of valid control signal sequences at the plurality of input/output pins so as to interface with the plurality of different types of flash memory for data exchange.

17. The interface of claim 16 wherein the plurality of memories comprise a first type flash memory and a second type flash memory, and wherein the first type flash memory is controlled by a first control signal sequence and the second type flash memory is controlled by a second control signal sequence, the finite state machine responding to a host processor request for access to one of the first and second types of flash memory by generating the corresponding control signal sequence at the input/output pins to interface with the requested flash memory.