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FLASH MEMORY INTERFACE DEVICE

  • US 20080052448A1
  • Filed: 07/19/2007
  • Published: 02/28/2008
  • Est. Priority Date: 07/20/2006
  • Status: Active Grant
First Claim
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1. A memory interface module interfacing between a host processor and a plurality of flash memories, the plurality of flash memories obeying a plurality of protocols, said memory interface module comprising:

  • a plurality of register files receiving a command from the host processor to control an operation of the plurality of flash memories and a plurality of parallel interfaces;

    a plurality of operation information registers for executing and storing the command and an operation information;

    an internal memory receiving and storing host data from the host processor and storing flash data extracted from the plurality of flash memories to transmit to the host processor;

    a flash interface portion performing a plurality of tasks, said tasks comprising;

    controlling a control signal to operate the plurality of flash memories;

    outputting one or more of the command, the operation information, and the host data; and

    controlling a data bus for enabling data transfer to the plurality of flash memories; and

    a finite state machine (FSM) extracting the command and the operation information and controlling the internal memory and the flash interface portion to execute the command, said memory interface module provides a flexibility to control the control signal through a plurality of pre-defined states, and said finite state machine (FSM) generating the control signal, such that the plurality of pre-defined states and their transitions being controlled by an user.

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