MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM

• US 20080052449A1
• Filed: 08/17/2007
• Published: 02/28/2008
• Est. Priority Date: 08/22/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Oh, HakJune, Pyeon, Hong Beom, KIM, Jin-Ki
• Granted Patent: US 7,904,639 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

Claims

1. A command structure comprising:

a plurality of separatable commands representing a request for access to one of a plurality of memory devices, each of the plurality of separate commands including;

a device identifier comprising an address for the one of a plurality of memory devices and an bank address for one of a plurality of memory banks in the one of the plurality of memory devices; and

a command identifier comprising an operation code representing an operation to be performed by the one of the plurality of memory devices.

2. The command structure of claim 1, wherein the one memory device comprises at least one memory bank, the address identifier comprising and a device address for one of the at least one memory devices and a bank address for one of the at least one memory banks.

3. The command structure of claim 2, wherein the address identifier comprises an m-byte identifier, m being an integer.

4. The command structure of claim 3, wherein the device address comprises an n-bit address and the bank address comprises a p-bit address, each of n and p being an integer.

5. The command structure of claim 1, wherein the command identifier comprises a q-byte command identifier, q being an integer.

6. The command structure of claim 1, wherein the modular structure further comprises a row address specifying a row in a memory bank of the at least one memory device to which the operation in the command identifier is to be applied.

7. The command structure of claim 1, wherein the modular structure further comprises a row address when the operation is of a determined type, the row address specifying a row in a memory bank of the at least one memory device to which the operation in the command identifier is to be applied.

8. The command structure of claim 6, wherein the row address comprises an r-byte address, r being an integer.

9. The command structure of claim 1, wherein the modular structure further comprises a column address specifying a column in a memory bank of the at least one memory device to which the operation in the command identifier is to be applied.

10. The command structure of claim 1, wherein the modular structure further comprises a column address when the operation is of a determined type, the column address specifying a column in a memory bank of the at least one memory device to which the operation in the command identifier is to be applied.

11. The command structure of claim 9, wherein the column address comprises an s-byte address, s being an integer.

12. The modular command structure of claim 11, wherein the one memory device comprises at least one memory bank, the address identifier comprising a device address for one of the at least one memory device and a bank address for one of the at least one memory bank.

13. The modular command structure of claim 12, wherein the command identifier comprises a q-byte identifier, q being an integer.

14. The modular command structure of claim 12, wherein the modular structure further comprises a row address specifying a row in a memory bank of the at least one memory device to which the operation in the command identifier is to be applied.

15. The modular command structure of claim 12, wherein the modular structure further comprises a row address when the operation is of a determined type, the row address specifying a row in a memory bank of the at least one memory device to which the operation in the command identifier is to be applied.

16. The modular command structure of claim 15, wherein the row address comprises an r-byte address, r being an integer.

17. The modular command structure of claim 12, wherein the modular structure further comprises a column address specifying a column in a memory bank of the at least one memory device to which the operation in the command identifier is to be applied.

18. The modular command structure of claim 12, wherein the modular structure further comprises a column address when the operation is of a determined type, the column address specifying a column in a memory bank of the at least one memory device to which the operation in the command identifier is to be applied.

19. The command structure of claim 4, wherein:

the m-byte identifier comprises a one-byte identifier;

the n-bit address comprises an six-bit address; and

the p-bit address comprises a two-bit address.

20. The command structure of claim 8, wherein the r-byte row address comprises a three-byte address

21. The command structure of claim 5, wherein the q-byte command identifier comprises a one-byte operation code.

22. A modular command structure comprising:

a device identifier comprising an address for one of a plurality of memory devices and an bank address for one of a plurality of memory banks in the one of the plurality of memory devices; and

a command identifier comprising an operation code representing an operation to be performed by the one of the plurality of memory devices.

23. A system comprising:

a memory system including at least one memory device for storing data;

a processor for managing requests for access to the memory system; and

a controller for translating the requests from the processor to one or more separatable commands interpretable by the at least one memory device, each command having a modular structure comprising an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices;

the at least one memory device and the controller being in a series-connection for communication.

24. The system of claim 23, wherein the at least one memory device comprises at least one memory bank, the address identifier including a device address for one of the at least one memory devices and a bank address for one of the at least one memory banks.

25. The system of claim 24, wherein the controller generates one or more separatable commands for different memory devices and interleaves issuance these one or more separatable commands for different memory devices.

26. The system of claim 25, wherein the at least one memory device includes at least two memory banks and the controller generates one or more separatable commands for each of the at least two memory banks and interleaves issuance of these one or more separatable commands so that the at least two memory banks are concurrently processing the issued one or more separatable commands.

27. The system of claim 23, wherein the memory devices in the memory system are connected to a common bus.

28. The system of claim 23, wherein the memory devices in the memory system are series-connected.

29. The system of claim 23, wherein the memory device comprises a NAND flash memory device.

30. A controller for a system having a plurality of memory devices for storing data, the controller being in a series-interconnection configuration for communication with the plurality of memory devices, the controller comprising:

a first connection for receiving requests for access to the plurality of memory devices;

a translator for translating the requests to a plurality of separatable commands interpretable by the plurality of memory devices, each command having a modular structure comprising an address identifier for one of the plurality of memory devices and a command identifier representing an operation to be performed by the one of the plurality of memory devices; and

a second connection for communication with one of the plurality of memory devices for issuing the plurality of separatable commands.

31. A method comprising:

determining an address including a memory device address;

identifying a plurality of operations effecting a request for access to a memory; and

providing a plurality of separatable commands for the memory, each of the commands including a device identifier having a memory device address and a command identifier having one of the plurality of operations.

32. The method of claim 31, being for translating a request for access to a memory device into a plurality of separatable commands interpretable by the memory device, wherein:

the step of determining comprises determining an address for the memory device and an address for a memory bank of the memory device;

the step of identifying comprises identifying a plurality of operations that in combination effect the request;

the step of providing comprises providing the plurality of separatable commands with each command comprising a device identifier including the memory device address and the memory bank address and a command identifier comprising one of the plurality of operations, where the command identifier is interpretable by the memory device, the plurality of separatable commands being issued to the memory device.

33. The method of claim 31, wherein:

the step of providing further comprises;

generating an m-byte device identifier, m being an integer.

generating an n-bit memory device address and a p-bit memory bank address, each of n and p being an integer; and

generating a q-byte command identifier, q being an integer, further comprising

interleaving issuance of each of the plurality of separatable commands having different device identifiers.

34. The method of claim 31, wherein the memory device comprises at least two memory banks, the method concurrently controlling the at least two memory banks,

the step of determining comprising determining an address for the memory device and an address for each of the at least two memory banks;

the step of identifying comprising identifying a plurality of operations that in combination effect a request for access to each of the at least two memory banks;

the step of providing comprising generating the plurality of separatable commands for each of the at least two memory banks, each of the plurality of separatable commands being issued to the memory device.

35. The method of claim 31, being for interleaving requests for access to a plurality of memory devices, wherein:

the step of determining comprises an address for each of the plurality of memory devices;

the step of identifying comprises identifying a plurality of operations that in combination effect each request;

the step of providing comprises generating a plurality of separatable commands for each request for each of the plurality of memory devices with each command including a device identifier having the memory device address and a command identifier having one of the plurality of operations, where the command identifier is interpretable by the memory device, each of the plurality of separatable commands being issued to the memory device.