FLASH STORAGE CHIP AND FLASH ARRAY STORAGE SYSTEM

• US 20080052451A1
• Filed: 10/30/2007
• Published: 02/28/2008
• Est. Priority Date: 03/14/2005
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Gan, Wee-Kuan, Pua, Khein-Seng, Wang, Chih-Ling
• Granted Patent: US 7,822,912 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A flash storage chip including a single circuit board, a microcontroller, a flash memory, and a peripheral component interconnect express (PCI Express) connecting interface is provided. The microcontroller, the flash memory, and the PCI Express connecting interface are embedded on the single circuit board, and the microcontroller has a flash memory interface and a PCI Express interface. When a host writes a data into the flash storage chip, the microcontroller receives the data though the PCI Express interface and stores the data into the flash memory though the flash memory interface. When the host reads a data form the flash storage chip, the microcontroller reads the data from the flash memory though the flash memory interface and transmits the data to the host though the PCI Express interface and the PCI Express connecting interface.

Claims

1. A flash array storage system, comprising:

a plurality of flash storage chips, arranged as an array, wherein each of the flash storage chips comprises;

a single circuit board;

a microcontroller, embedded on the single circuit board, having a flash memory interface and a PCI Express interface;

at least one flash memory, embedded on the single circuit board and coupled to the microcontroller for storing data; and

a PCI Express connecting interface, embedded on the single circuit board and coupled to the microcontroller;

a flash array controller, coupled to the flash storage chips for controlling data access to the flash storage chips; and

a data transmission interface, coupled to the flash array controller for connecting to a host and transmitting instructions and data between the host and the flash array storage system;

wherein when the host writes a data into the flash array storage system, the flash array controller designates at least one of the flash storage chips to write the data, and the microcontroller of the designated flash storage chip receives the data through the PCI Express connecting interface and the PCI Express interface and writes the data into the flash memory through the flash memory interface,

wherein when the host reads a data from the flash array storage system, the flash array controller searches for the flash storage chip which stores the data, and the microcontroller of the flash storage chip which stores the data reads the data from the flash memory through the flash memory interface and transmits the data through the PCI Express interface and the PCI Express connecting interface.

2. The flash array storage system according to claim 1, wherein the at least one flash memory in each of the flash storage chips is a single level cell (SLC) NAND flash memory or a multi level cell (MLC) NAND flash memory.

3. The flash array storage system according to claim 1, wherein the microcontroller and the at least one flash memory in each of the flash storage chips are embedded on the single circuit board through quad flat no lead (QFN) packaging, land grid array (LGA) packaging, ball grid array (BGA) packaging, low profile quad flat packaging (LQFP), quad flat packaging (QFP), die packaging, chip on board (COB) packaging, or system in package (SIP).

4. The flash array storage system according to claim 1, wherein a transmitter Tx and a receiver Rx are constituted by at least one simplex channel at a physical layer for data transmission between the flash array controller and the flash storage chips.

5. A flash array storage system, comprising:

a plurality of flash storage chips, arranged as an array, each of the flash storage chips comprising;

a single circuit board;

a microcontroller, embedded on the single circuit board and having a flash memory interface, a PCI Express interface, and a virtual integrated device electronics (IDE) module, the virtual IDE module having an IDE master port for receiving an IDE instruction and an IDE device port for executing the IDE instruction, the virtual IDE module being implemented by a firmware which can be executed by the microcontroller;

at least one flash memory, embedded on the single circuit board and coupled to the microcontroller for storing data; and

a PCI Express connecting interface, embedded on the single circuit board and coupled to the microcontroller for connecting to a host; and

a flash array driving program, installed in the host and executed by the host for controlling data access to the flash storage chips;

wherein when the host reads a data from the flash array storage system, the flash array driving program searches for the flash storage chip which stores the data, and the virtual IDE module of the flash storage chip which stores the data receives and executes the IDE instruction issued by the host, and the data is read by the flash memory interfaces and converted into formats acceptable to the PCI Express connecting interfaces by the PCI Express interfaces to be transmitted,

wherein when the host writes a data into the flash array storage system, the flash array driving program designates at least one of the flash storage chips to write the data, and the virtual IDE module of the designated flash storage chip receives and executes the IDE instruction issued by the host, and the data is received by the PCI Express connecting interface and the PCI Express interface and converted into formats acceptable to the flash memories by the flash memory interfaces to be written into the flash memories.

6. The flash array storage system according to claim 5, wherein the at least one flash memory in each of the flash storage chips is a SLC NAND flash memory or a MLC NAND flash memory.

7. The flash array storage system according to claim 5, wherein the microcontroller and the at least one flash memory in each of the flash storage chips are embedded on the single circuit board through QFN packaging, LGA packaging, BGA packaging, LQFP, QFP, die packaging, COB packaging, or SIP.

8. The flash array storage system according to claim 5, wherein the IDE instruction is compatible to ATA specification or serial ATA specification.

9. A flash storage chip, comprising:

a single circuit board;

a microcontroller, embedded on the single circuit board, having a flash memory interface and a PCI Express interface;

at least one flash memory, embedded on the single circuit board and coupled to the microcontroller for storing data; and

a PCI Express connecting interface, embedded on the single circuit board and coupled to the microcontroller for coupling the flash storage chip to a host,

wherein when the host writes a data into the flash storage chip, the microcontroller receives the data through the PCI Express interface and writes the data into the flash memory through the flash memory interface,

wherein when the host reads a data from the flash storage chip, the microcontroller reads the data from the flash memory through the flash memory interface and transmits the data to the host through the PCI Express interface and the PCI Express connecting interface.

10. The flash storage chip according to claim 9, wherein the at least one flash memory is a SLC NAND flash memory or a MLC NAND flash memory.

11. The flash storage chip according to claim 9, wherein the microcontroller and the at least one flash memory are embedded on the single circuit board through QFN packaging, LGA packaging, BGA packaging, LQFP, QFP, die packaging, COB packaging, or SIP.

12. The flash storage chip according to claim 11, wherein the pins of the packaged flash storage chip comprise at least a PERST# pin, a REFCLK+ pin, a REFCLK−

pin, a PETp0 pin, a PETn0 pin, a PERp0 pin, a PERn0 pin, a Power pin, and a Ground pin.

13. A flash storage chip, comprising:

a single circuit board;

a microcontroller, embedded on the single circuit board and having a flash memory interface, a PCI Express interface, and a virtual IDE module, the virtual IDE module having an IDE master port for receiving an IDE instruction and an IDE device port for executing the IDE instruction, the virtual IDE module being implemented by a firmware which can be executed by the microcontroller;

at least one flash memory, embedded on the single circuit board and coupled to the microcontroller for storing data; and

a PCI Express connecting interface, embedded on the single circuit board and coupled to the microcontroller for coupling the flash storage chip to the host, wherein when the host reads a data from the flash memory, the IDE instruction issued by the host is transmitted to the virtual IDE module to be executed by the virtual IDE module, and the data is read from the flash memory through the flash memory interface and converted into a format acceptable to the PCI Express connecting interface through the PCI Express interface to be transmitted to the host,

wherein when the host writes a data into the flash memory, the IDE instruction issued by the host is transmitted to the virtual IDE module to be executed by the virtual IDE module, and the data is received through the PCI Express interface and converted into a format acceptable to the flash memory through the flash memory interface to be written into the flash memory.

14. The flash storage chip according to claim 13, wherein the at least one flash memory is a SLC NAND flash memory or a MLC NAND flash memory.

15. The flash storage chip according to claim 13, wherein the microcontroller and the at least one flash memory are embedded on the single circuit board through QFN packaging, LGA packaging, BGA packaging, LQFP, QFP, die packaging, COB packaging, or SIP.

16. The flash storage chip according to claim 13, wherein the IDE instruction is compatible to ATA specification or serial ATA specification.

17. A flash storage chip, comprising:

a single circuit board;

a microcontroller, embedded on the single circuit board and having a flash memory interface and a PCI Express interface;

a plurality of flash memories, embedded on the single circuit board and respectively coupled to the microcontroller for storing data; and

a PCI Express connecting interface, embedded on the single circuit board and coupled to the microcontroller for coupling the flash storage chip to a host,

wherein when the host writes a data into the flash storage chip, the microcontroller receives the data through the PCI Express interface and writes the data into the flash memories through the flash memory interface,

wherein when the host reads a data from the flash storage chip, the microcontroller reads the data from the flash memories through the flash memory interface and transmits the data to the host through the PCI Express interface and the PCI Express connecting interface,

wherein the data is read from or written into the flash memories in a parallel manner.

18. The flash storage chip according to claim 17, wherein each of the flash memories is a SLC NAND flash memory or a MLC NAND flash memory.

19. The flash storage chip according to claim 17, wherein the microcontroller and the flash memories are embedded on the single circuit board through QFN packaging, LGA packaging, BGA packaging, LQFP, QFP, die packaging, COB packaging, or SIP.

20. The flash storage chip according to claim 19, wherein the pins of the packaged flash storage chip comprise at least a PERST# pin, a REFCLK+ pin, a REFCLK−

pin, a PETp0 pin, a PETn0 pin, a PERp0 pin, a PERn0 pin, a Power pin, and a Ground pin.

21. The flash storage chip according to claim 17, wherein a transmitter Tx and a receiver Rx are constituted by at least one simplex channel at a physical layer for data transmission between the host and the flash storage chip.

22. The flash storage chip according to claim 17, wherein the microcontroller further comprises a virtual IDE module, the virtual IDE module has an IDE master port for receiving an IDE instruction and an IDE device port for executing the IDE instruction, and the virtual IDE module is implemented by a firmware which can be executed by the microcontroller.