Method and apparatus to implement cache-coherent network interfaces

• US 20080052463A1
• Filed: 08/25/2006
• Published: 02/28/2008
• Est. Priority Date: 08/25/2006
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bradford, Dennis R., Stillwell, Paul M., Rankin, Linda J., Chitlur, Nagabhushan
• Application Number:
  US11/510,021
• Publication Number:
  US 20080052463A1
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A cache-coherent network interface includes registers or buffers addressable by a processor with reference to an address space of the processor. The processor and the cache-coherent network interface both share a common system bus. The registers or buffers are further cacheable into a cache of the processor with reference to the address space.

Claims

1. A method, comprising:

addressing registers or buffers of a network interface within address space of a processor; and

caching content in the registers or buffers into a cache of the processor with reference to the address space of the processor.

2. The method of claim 1, wherein the network interface is coupled to and addressable on a system bus of the processor, and wherein caching the content comprises transferring the content from the registers or buffers into the cache without first transferring the content to system memory of the processor.

3. The method of claim 2, wherein the network interface comprises a cache-coherent network interface and the registers or buffers comprise cacheable memory addressed in the address space of the processor.

4. The method of claim 3, wherein the registers or buffers include at least one of a control and status registers (“

CSRs”

), transmit descriptor buffers, receive descriptor buffers, or receive data buffers, wherein;

the CSRs are accessible to the processor via a CSR aperture included in an address map of the processor,

the transmit descriptor buffers are accessible to the processor via a transmit descriptor aperture included in the address map of the processor,

the receive descriptor buffers are accessible to the processor via a receive descriptor aperture included in the address map of the processor, and

the receive data buffers are accessible to the processor via a receive data aperture included within the address map of the processor.

5. The method of claim 1, further comprising:

receiving data from a network at the network interface;

buffering the data at the network interface in a receive data buffer; and

reading the data from the receive data buffer into the cache under control of the processor by addressing the receive data buffer with reference to the address space of the processor.

6. The method of claim 1, further comprising:

creating a command in the cache of the processor; and

evicting the command from the cache into a descriptor buffer physically located in the network interface, wherein the descriptor buffer is addressable via the address space of the processor.

7. The method of claim 6, wherein the descriptor buffer comprises a receive descriptor buffer, the method further comprising:

buffering data received from a network coupled to the network interface in a receive data buffer;

executing the command from the receive descriptor buffer with a direct memory access (“

DMA”

) engine of the network interface, and

transferring the data buffered in the receive data buffer onto a front side bus of the processor coupled to the network interface under control of the DMA engine in response to executing the command.

8. The method of claim 6, wherein the descriptor buffer comprises a transmit descriptor buffer, the method further comprising:

transferring data from the cache into the transmit descriptor buffer;

executing the command from the transmit descriptor buffer with a memory transfer engine of the network interface; and

transmitting the data in the transmit descriptor buffer onto the network under control of the memory transfer engine in response to executing the command.

9. The method of claim 1, further comprising:

caching control and status register (“

CSR”

) content of the network interface in the cache of the processor;

invalidating a portion of the cache caching the CSR content when the CSR content changes; and

updating the cache when with new CSR content when the CSR content changes.

10. An apparatus, comprising:

a system bus;

a processor coupled to the system bus, the processor including a cache; and

a network interface coupled to the system bus, the network interface including registers or buffers addressable by the processor via an address space of the processor.

11. The apparatus of claim 10, wherein the network interface is addressable on the system bus.

12. The apparatus of claim 11, wherein the network interface comprises a cache-coherent network interface and the registers or buffers comprise cacheable memory addressed in the address space of the processor and cacheable in the cache of the processor.

13. The apparatus of claim 11, wherein the network interface is coupled to the system bus to cache content of the registers or buffers in the cache of the processor, the apparatus further comprising:

a cache coherency agent coupled to maintain cache coherency between the cache of the processor and the registers or buffers.

14. The apparatus of claim 10, wherein the registers or buffers of the network interface include a receive data buffer to buffer network data received from a network and a receive descriptor buffer coupled to buffer receive commands written from the processor, the apparatus further comprising:

a memory transfer engine coupled to the receive descriptor buffer and to the receive data buffer to execute the receive commands buffered in the receive descriptor buffer and to direct memory access (“

DMA”

) transfer the network data into system memory of the processor in response to the receive commands, wherein the memory transfer engine transmits the network data directly onto the system bus.

15. The apparatus of claim 14, wherein the registers or buffers of the network interface further includes a transmit descriptor buffer coupled to the memory transfer engine, the transmit descriptor buffer coupled to buffer immediate data and transmit commands, the memory trasnfer engine coupled to transmit the immediate data onto the network in response to executing the transmit commands, wherein the processor is coupled to write the immediate data and the transmit commands into the transmit descriptor buffer without first transferring the immediate data and the transmit commands into the system memory.

16. The apparatus of claim 10, wherein the registers or buffers of the network interface include control and status registers addressable by the processor via the address space of the processor.

17. The apparatus of claim 10, wherein the network interface comprises a network interface card (“

NIC”

) and the system bus comprises one of a front side bus, a HyperTransport interconnect, or a Common System Interconnect (“

CSI”

).

18. The apparatus of claim 10, wherein the network interface further includes an internal cache for caching data received from a network, wherein the cache is accessible to the processor as an extension of system memory.

19. A system, comprising:

a system interconnect;

synchronous dynamic random access memory (“

SDRAM”

) linked to the system interconnect, the SDRAM to store instructions;

a processor coupled to the system interconnect to receive and execute the instructions; and

a network interface coupled to the system interconnect, the network interface including registers or buffers addressable by the processor via an address space of the processor.

20. The system of claim 19, wherein the network interface comprises a cache-coherent network interface card (“

NIC”

) addressable on the system bus and wherein the registers or buffers of the cache-coherent NIC comprise cacheable memory addressed in the address space of the processor.

21. The system of claim 20, wherein the cache-coherent NIC is coupled to the system interconnect to cache content of the registers or buffers in a cache of the processor, the system further comprising:

a cache coherency agent coupled to maintain cache coherency between the cache of the processor and the registers or buffers.

22. The system of claim 19, wherein the registers or buffers of the network interface include control and status registers addressable by the processor via the address space of the processor.

23. The system of claim 19, further including a plurality of processors coupled to the system interconnect, wherein the registers or buffers of the network interface are addressable by each of the plurality of processors via their respective address spaces.