INFORMATION PROCESSING APPARATUS
First Claim
1. An information processing apparatus comprising a processor, a plurality of storage devices, and a system controller which controls the plurality of storage devices, wherein the system controller comprises a unit which divides data of processor bus width from the processor into a plurality of divided data, a first transfer unit which simultaneously and in parallel transfers the plurality of divided data to the plurality of storage devices distributing them, a second transfer unit which sequentially transfers the plurality of divided data to the same storage device, and a mode control unit which operates either the first transfer unit or the second transfer unit.
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Accused Products
Abstract
A system controller which controls a plurality of storage devices comprises a unit which divides data of processor bus width from a processor into a plurality of divided data, a first transfer unit which simultaneously transfers the divided plurality of divided data to the plurality of storage devices distributing them, a second transfer unit which time divides the divided plurality of divided data and sequentially transfers them to the same storage device, and a mode control unit which operates either the first transfer unit or the second transfer unit.
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Citations
10 Claims
- 1. An information processing apparatus comprising a processor, a plurality of storage devices, and a system controller which controls the plurality of storage devices, wherein the system controller comprises a unit which divides data of processor bus width from the processor into a plurality of divided data, a first transfer unit which simultaneously and in parallel transfers the plurality of divided data to the plurality of storage devices distributing them, a second transfer unit which sequentially transfers the plurality of divided data to the same storage device, and a mode control unit which operates either the first transfer unit or the second transfer unit.
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8. An information processing apparatus comprising a processor, a plurality of storage devices, and a system controller which controls the plurality of storage devices, wherein the system controller comprises a plurality of write data buffers which divide data of processor bus width from the processor into a plurality of divided data and store them, a plurality of first selectors corresponding to each storage device which selects divided data to transfer to each storage device from the divided data read out from the plurality of write data buffers, a mode register which designates an operation mode of said information processing apparatus, and a mode control part which controls an access to the plurality of storage devices according to an instruction of the mode register,
the mode control part, when a high performance mode is designated, reads out simultaneously the plurality of divided data from the plurality of write data buffers, makes the first selectors select the plurality of divided data simultaneously read out, and simultaneously transfers selected plurality of divided data to corresponding plurality of storage devices, and when a high reliability mode is designated, sequentially reads out the divided data from the plurality of write data buffers, makes the first selectors sequentially select the divided data sequentially read out, and sequentially transfers selected divided data to each storage device.
Specification