Systems and methods for secure transaction management and electronic rights protection
2 Assignments
0 Petitions
Accused Products
Abstract
The present invention provides systems and methods for electronic commerce including secure transaction management and electronic rights protection. Electronic appliances such as computers employed in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Secure subsystems used with such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Secure distributed and other operating system environments and architectures, employing, for example, secure semiconductor processing arrangements that may establish secure, protected environments at each node. These techniques may be used to support an end-to-end electronic information distribution capability that may be used, for example, utilizing the “electronic highway.”
209 Citations
89 Claims
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1-18. -18. (canceled)
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19. A secure processing unit comprising a processor and security-relevant components, said security-relevant components including:
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an encryption/decryption engine;
a random number generator;
secure memory;
secure processor mode-enabling hardware and/or software configured to cause said processor to enter a secure processor mode, said secure processor mode-enabling hardware and/or software including;
component-accessing hardware and/or software configured to provide said processor with access to at least a portion of said secure memory and/or other of said security-relevant components while said processor operates in said secure processor mode;
secure code execution hardware and/or software configured to cause said processor to fetch and execute instructions from said secure memory while said processor operates in said secure processor mode;
secure processor mode-disabling hardware and/or software configured to cause said processor to exit said secure processor mode, said secure processor mode-disabling hardware and/or software including hardware and/or software configured to block access to at least a portion of said secure memory and/or other of said security-relevant components while said processor does not operate in said secure processor mode. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. An electronic appliance, the electronic appliance comprising:
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a secure processing unit, the secure processing unit comprising;
a processor;
internal memory;
secure processor mode-enabling hardware and/or software configured to cause said processor to enter a secure processor mode, said secure processor mode-enabling hardware and/or software including;
accessing hardware and/or software configured to provide said processor with access to at least a portion of said internal memory while said processor operates in said secure processor mode;
secure code execution hardware and/or software configured to cause said processor to fetch and execute instructions from said internal memory while said processor operates in said secure processor mode;
secure processor mode-disabling hardware and/or software configured to cause said processor to exit said secure processor mode, said secure processor mode-disabling hardware and/or software including hardware and/or software configured to block access to at least a portion of said internal memory while said processor does not operate in said secure processor mode. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. A processing unit comprising:
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a processor;
internal memory;
secure processor mode-enabling hardware and/or software configured to cause said processor to enter a secure processor mode, said secure processor mode-enabling hardware and/or software including;
accessing hardware and/or software configured to provide said processor with access to at least a portion of said internal memory while said processor operates in said secure processor mode;
secure code execution hardware and/or software configured to cause said processor to fetch and execute instructions from said internal memory while said processor operates in said secure processor mode;
secure processor mode-disabling hardware and/or software configured to cause said processor to exit said secure processor mode, said secure processor mode-disabling hardware and/or software including hardware and/or software configured to block access to at least a portion of said internal memory while said processor does not operate in said secure processor mode. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A processing unit comprising:
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a processor;
internal memory;
secure processor mode-enabling means for causing said processor to enter a secure processor mode, said secure processor mode-enabling means including;
means for providing said processor with access to at least a portion of said internal memory while said processor operates in said secure processor mode;
means for causing said processor to fetch and execute instructions from said internal memory while said processor operates in said secure processor mode;
secure processor mode-disabling means for causing said processor to exit said secure processor mode, said secure processor mode-disabling means including means for blocking access to at least a portion of said internal memory while said processor does not operate in said secure processor mode. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56)
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57. A method performed by a processing unit, the processing unit comprising:
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a processor;
internal memory;
secure processor mode-enabling hardware and/or software configured to cause said processor to enter a secure processor mode, said secure processor mode-enabling hardware and/or software including;
hardware and/or software configured to provide said processor with access to at least a portion of said internal memory while said processor operates in said secure processor mode; and
secure processor mode-disabling hardware and/or software configured to cause said processor to exit said secure processor mode, said secure processor mode-disabling hardware and/or software including hardware and/or software configured to block access to at least a portion of said internal memory while said processor is not operating in said secure processor mode;
the method comprising;
entering said secure processor mode;
accessing at least a portion of the internal memory while said processor is operating in the secure processor mode; and
exiting the secure processor mode. - View Dependent Claims (58, 59, 60, 61, 62, 63, 64, 65, 66)
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67. A processing unit comprising:
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a processor;
a tamper-resistant barrier operable to render unauthorized interference with, or access to, the contents or operations of the processing unit more difficult;
a clock;
an encryption/decryption engine;
a random number generator;
a compression/decompression engine;
memory storing one or more cryptographic keys; and
means for applying control information to govern usage of one or more secure objects, the secure objects comprising electronic content. - View Dependent Claims (68, 69, 70, 71, 72, 73, 74, 75, 76, 77)
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78. A system comprising:
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a processing unit comprising;
a processor;
a tamper-resistant barrier operating to render unauthorized interference with, or access to, the contents or operations of the processing unit more difficult;
a clock;
an encryption/decryption engine;
a random number generator;
a compression/decompression engine; and
memory storing one or more cryptographic keys;
means for swapping blocks of data to and from said processing unit; and
means for integrity verification of said blocks of data. - View Dependent Claims (79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89)
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Specification