MEMORY MULTI-BIT ERROR CORRECTION AND HOT REPLACE WITHOUT MIRRORING

• US 20080052598A1
• Filed: 08/09/2006
• Published: 02/28/2008
• Est. Priority Date: 08/09/2006
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Assimos, Charles, Medina, Cristian, Aksamit, Slavek P.
• Application Number:
  US11/463,393
• Publication Number:
  US 20080052598A1
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

The invention is directed to memory multi-bit error correction and hot replace without mirroring. A memory configuration in accordance with an embodiment of the present invention includes: a plurality of memory modules; a memory controller for reading/writing data from/into the memory modules; and an error correcting memory module for storing an error correcting code for each address contained in the plurality of memory modules.

Claims

1. A memory configuration, comprising:

a plurality of memory modules;

a memory controller for reading/writing data from/into the memory modules; and

an error correcting memory module for storing an error correcting code for each address contained in the plurality of memory modules.

2. The memory configuration of claim 1, further comprising:

a multiplexer associated with each memory module for determining which of a plurality of memory components on the memory module has access to a data bus.

3. The memory configuration according to claim 1, wherein one of the plurality of memory modules can be hot-replaced using the error correcting code stored on the error correcting memory module, without requiring memory mirroring.

4. The memory configuration according to claim 1, wherein an error caused by a failure or removal of one of the plurality of memory modules can be corrected using the error correcting bits stored on the error correcting memory module, without requiring memory mirroring.

5. A method for error correction, comprising:

splitting data into segments;

reading/writing each data segment from/into a different one of a plurality of memory modules;

storing an error correcting code in an error correcting memory module for each address contained in the plurality of memory modules; and

correcting an error caused by a removal or failure of one of the plurality of memory modules using the error correcting code stored in the error correcting memory module, without requiring memory mirroring.

6. The method of claim 5, further comprising:

hot-replacing one of the plurality of memory modules using the error correcting code stored on the error correcting memory module, without requiring memory mirroring.