Data corruption avoidance in DRAM chip sparing
First Claim
1. A method comprising:
- reading data from a given location of one or more of a plurality of memory chips including a first memory chip, wherein each of the plurality of memory chips is configured to store data at a plurality of locations;
writing the data read from the given location of the one or more of the plurality of memory chips including a first memory chip to the given location of one or more of the plurality of memory chips including a second memory chip, wherein during said writing, data from the first memory chip is written to the second memory chip; and
allowing additional memory transactions directed to the plurality of memory chips between a start of said reading and an end of said writing unless the additional memory transaction is targeted to the given location.
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Accused Products
Abstract
A memory controller, system, and methods are disclosed. The system comprises a memory controller interconnected to a plurality of memory chips. Each memory chip stores data at a plurality of locations. The memory controller performs a sparing transaction comprising reading data from a given location of one or more of the memory chips including a first memory chip, writing the data to a given location of one or more of the memory chips including a second memory chip, wherein during writing, data from the first memory chip is written to the second memory chip, and allowing additional memory transactions directed to the memory chips between the start of reading and the end of writing unless the additional memory transaction is targeted to the given location. In a further embodiment, the sparing transaction comprises correcting errors in the data before writing the data.
28 Citations
20 Claims
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1. A method comprising:
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reading data from a given location of one or more of a plurality of memory chips including a first memory chip, wherein each of the plurality of memory chips is configured to store data at a plurality of locations; writing the data read from the given location of the one or more of the plurality of memory chips including a first memory chip to the given location of one or more of the plurality of memory chips including a second memory chip, wherein during said writing, data from the first memory chip is written to the second memory chip; and allowing additional memory transactions directed to the plurality of memory chips between a start of said reading and an end of said writing unless the additional memory transaction is targeted to the given location. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system comprising:
a memory controller interconnected to a plurality of memory chips, wherein each memory chip is configured to store data at a plurality of locations, and wherein the memory controller is configured to perform a sparing transaction comprising; reading data from a given location of one or more of the plurality of memory chips including a first memory chip; writing the data read from the given location of the one or more of the plurality of memory chips including a first memory chip to the given location of one or more of the plurality of memory chips including a second memory chip, wherein during said writing, data from the first memory chip is written to the second memory chip; and allowing additional memory transactions directed to the plurality of memory chips between a start of said reading and an end of said writing unless the additional memory transaction is targeted to the given location. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A memory controller for communicating with a plurality of memory chips, wherein each memory chip is configured to store data at a plurality of locations, and wherein the memory controller is configured to perform a sparing transaction comprising:
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reading data from a given location of one or more of the plurality of memory chips including a first memory chip; writing the data read from the given location of the one or more of the plurality of memory chips including a first memory chip to the given location of one or more of the plurality of memory chips including a second memory chip, wherein during said writing, data from the first memory chip is written to the second memory chip; and allowing additional memory transactions directed to the plurality of memory chips between a start of said reading and an end of said writing unless the additional memory transaction is targeted to the given location. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification