METHOD AND APPARATUS FOR ERROR DETECTION IN A DATA BLOCK

• US 20080052603A1
• Filed: 08/14/2006
• Published: 02/28/2008
• Est. Priority Date: 08/14/2006
• Status: Active Grant

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bohn, Thomas B., Wiatrowski, David G., Doberstein, Kevin G., Newberg, Donald G.
• Granted Patent: US 7,500,170 B2
• Time in Patent Office: Days
• US Class Current: 714/776
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0083 Formatting with frames or packets; Protocol or part of protocol for error control

Abstract

A transmitting device generates a data block including a first field having a first plurality of bits that includes an error detection portion and a second field having a second plurality of bits; selects an error injection mask based on the second plurality of bits; modifies the first plurality of bits with the error injection mask to generate a modified first plurality of bits; and transmits the data block to a receiving device. The receiving device decodes the second plurality of bits to generate decoding results; selects an error injection mask based on the decoding results; modifies the first plurality of bits using the error injection mask to generate a modified first plurality of bits that includes a resultant error detection value indicated in the error detection portion; and detects whether the decoding results for the second field are correct based on the resultant error detection value.

Claims

1. A method for error detection in a data block, comprising the steps of:

generating a data block comprising a first field having a first plurality of bits that includes an error detection portion indicating an error detection value based on a first portion of the first plurality of bits and used for error detection in decoding the first portion of the first plurality of bits, and the data block further comprising at least a second field having a second plurality of bits;

selecting an error injection mask based on the second plurality of bits;

modifying the first plurality of bits with the error injection mask to generate a modified first plurality of bits that is used for error detection in decoding the second plurality of bits; and

transmitting the data block with the modified first plurality of bits.

2. The method of claim 1, wherein the data block comprises a digital mobile radio (DMR) Time Division Multiple Access (TDMA) burst as defined in ETSI (European Telecommunications Standards Institute) TS (Technical Specification) 102 361-1.

3. The method of claim 1, wherein:

the first field comprises information and the first plurality of bits comprises error detection bits and data bits of a first data type;

the second field comprises a data type field, and the second plurality of bits indicates the first data type; and

the error injection mask corresponds to the first data type.

4. The method of claim 3, wherein modifying the first plurality of bits comprises at least one of:

modifying the error detection bits; and

modifying the data bits.

5. The method of claim 4, wherein the error injection mask is selected from a group comprising:

00₁₆, 03₁₆, 0c₁₆, 0f₁₆;

30₁₆, 33₁₆, 3c₁₆, 3f₁₆;

55₁₆, 56₁₆, 59₁₆, 5a₁₆;

65₁₆, 66₁₆, 69₁₆, 6a₁₆;

95₁₆, 96₁₆, 99₁₆, 9a₁₆;

a5₁₆, a6₁₆, a9₁₆, aa₁₆;

c0₁₆, c3₁₆, cc₁₆, cf₁₆;

f0₁₆, f3₁₆, fc₁₆, ff₁₆;

000₈, 017₈, 063₈, 074₈;

125₈, 132₈, 146₈, 151₈;

226₈, 231₈, 245₈, 252₈;

303₈, 314₈, 360₈, 377₈;

400₈, 417₈, 463₈, 474₈;

525₈, 532₈, 546₈, 551₈;

626₈, 631₈, 645₈, 652₈;

703₈, 714₈, 760₈, 777₈;

0000₁₆, 00ff₁₆, 0f0f₁₆, 0ff0₁₆;

3333₁₆, 33cc₁₆, 3c3c₁₆, 3cc3₁₆;

5555₁₆, 55aa₁₆, 5a5a₁₆, 5aa5₁₆;

6666₁₆, 6699₁₆, 6969₁₆, 6996₁₆;

9669₁₆, 9696₁₆, 9966₁₆, 9999₁₆;

a55a₁₆, a5a5₁₆, aa55₁₆, aaaa₁₆;

c33c₁₆, c3c3₁₆, cc33₁₆, cccc₁₆;

f00f₁₆, f0f0₁₆, ff00₁₆, ffff₁₆;

000000₁₆, 00ff00₁₆, 0f0f0f₁₆, 0ff00f₁₆;

333333₁₆, 33cc33₁₆, 3c3c3c₁₆, 3cc33c₁₆;

555555₁₆, 55aa55₁₆, 5a5a5a₁₆, 5aa55a₁₆;

666666₁₆, 669966₁₆, 696969₁₆, 699669₁₆;

966996₁₆, 969696₁₆, 996699₁₆, 999999₁₆;

a55aa5₁₆, a5a5a5₁₆, aa55aa₁₆, aaaaaa₁₆;

c33cc3₁₆, c3c3c3₁₆, cc33CC₁₆, cccccc₁₆;

f00ff0₁₆, f0f0f0₁₆, ff00ff₁₆, ffffff₁₆;

00000000₁₆, 00ff00ff₁₆, 0f0f0f0f₁₆, 0ff00ff0₁₆;

33333333₁₆, 33cc33cc₁₆, 3c3c3c3c₁₆, 3cc333c3₁₆;

55555555₁₆, 55aa55aa₁₆, 5a5a5a5a₁₆, 5aa55aa5₁₆;

66666666₁₆, 66996699₁₆, 69696969₁₆, 69966996₁₆;

96699669₁₆, 96969696₁₆, 99669966₁₆, 99999999₁₆;

a55aa55a₁₆, a5a5a5a5₁₆, aa55aa55₁₆, aaaaaaaa₁₆;

c33cc33c₁₆, c3c3c3c3₁₆, cc33 cc33₁₆, cccccccc₁₆;

f00ff00f₁₆, f0f0f0f0₁₆, ff00ff00₁₆, ffffffff₁₆, for modifying the error detection bits.

6. The method of claim 1, wherein the error detection portion of the first plurality of bits comprises one of a Cyclic Redundancy Check, a Checksum and a Simple Parity Check.

7. The method of claim 1, wherein the error injection mask comprises a predetermined plurality of bits and modifying the first plurality of bits comprises combining the error injection mask with the first plurality of bits using bitwise modulo 2 addition.

8. The method of claim 1, wherein the data block further comprising at least a third field having a third plurality of bits, and the method further comprising the steps of:

selecting a second error injection mask based on the third plurality of bits; and

further modifying the first plurality of bits with the second error injection mask to generate the modified first plurality of bits that is further used for error detection in decoding the third plurality of bits.

9. A method for error detection in a data block, comprising the steps of:

receiving a data block comprising a first field having a first plurality of bits that includes an error detection portion indicating an error detection value, the data block further comprising at least a second field having a second plurality of bits;

decoding the second plurality of bits to generate decoding results;

selecting an error injection mask based on the decoding results;

modifying the first plurality of bits using the error injection mask to generate a modified first plurality of bits that includes a resultant error detection value; and

detecting whether the decoding results for the second field are correct based on the resultant error detection value indicated in the first field.

10. The method of claim 9, wherein detecting whether the decoding results for the second field are correct comprises the steps of:

calculating an error detection value based on at least a portion of the modified first plurality of bits; and

comparing the calculated error detection value to the resultant error detection value, wherein the decoding results for the second field are correct when the calculated error detection is equal to the resultant error detection value.

11. The method of claim 10, wherein the data block comprises a digital mobile radio (DMR) Time Division Multiple Access (TDMA) burst as defined in ETSI (European Telecommunications Standards Institute) TS (Technical Specification) 102 361-1.

12. The method of claim 10, wherein:

the first field comprises information and the first plurality of bits comprises error detection bits and data bits of a first data type;

the second field comprises a data type field, and the second plurality of bits indicates the first data type; and

the error injection mask corresponds to the first data type.

13. The method of claim 12, wherein modifying the first plurality of bits comprises at least one of:

modifying the error detection bits; and

modifying the data bits.

14. The method of claim 13, wherein the error injection mask is selected from a group comprising:

00₁₆, 03₁₆, 0c₁₆, 0f₁₆;

30₁₆, 33₁₆, 3c₁₆, 3f₁₆;

55₁₆, 56₁₆, 59₁₆, 5a₁₆;

65₁₆, 66₁₆, 69₁₆, 6a₁₆;

95₁₆, 96₁₆, 99₁₆, 9a₁₆;

a5₁₆, a6₁₆, a9₁₆, aa₁₆;

c0₁₆, c3₁₆, cc₁₆, cf₁₆;

f0₁₆, f3₁₆, fc₁₆, ff₁₆;

000₈, 017₈, 063₈, 074₈;

125₈, 132₈, 146₈, 151₈;

226₈, 231₈, 245₈, 252₈;

303₈, 314₈, 360₈, 377₈;

400₈, 417₈, 463₈, 474₈;

525₈, 532₈, 546₈, 551₈;

626₈, 631₈, 645₈, 652₈;

703₈, 714₈, 760₈, 777₈;

0000₁₆, 00ff₁₆, 0f0f₁₆, 0ff0₁₆;

3333₁₆, 33cc₁₆, 3c3c₁₆, 3cc3₁₆;

5555₁₆, 55aa₁₆, 5a5a₁₆, 5aa5₁₆;

6666₁₆, 6699₁₆, 6969₁₆, 6996₁₆;

9669₁₆, 9696₁₆, 9966₁₆, 9999₁₆;

a55a₁₆, a5a5₁₆, aa55₁₆, aaaa₁₆;

c33c₁₆, c3c3₁₆, cc33₁₆, cccc₁₆;

f00f₁₆, f0f0₁₆, ff00₁₆, ffff₁₆;

000000₁₆, 00ff00₁₆, 0f0f0f₁₆, 0ff00f₁₆;

333333₁₆, 33cc33₁₆, 3c3c3c₁₆, 3cc33c₁₆;

555555₁₆, 55aa55₁₆, 5a5a5a₁₆, 5aa55a₁₆;

666666₁₆, 669966₁₆, 696969₁₆, 699669₁₆;

966996₁₆, 969696₁₆, 996699₁₆, 999999₁₆;

a55aa5₁₆, a5a5a5₁₆, aa55aa₁₆, aaaaaa₁₆;

c33cc3₁₆, c3c3c3₁₆, cc33CC₁₆, cccccc₁₆;

f00ff0₁₆, f0f0f0₁₆, ff00ff₁₆, ffffff₁₆;

00000000₁₆, 00ff00ff₁₆, 0f0f0f0f₁₆, 0ff00ff0₁₆;

33333333₁₆, 33cc33cc₁₆, 3c3c3c3c₁₆, 3cc333c3₁₆;

55555555₁₆, 55aa55aa₁₆, 5a5a5a5a₁₆, 5aa55aa5₁₆;

66666666₁₆, 66996699₁₆, 69696969₁₆, 69966996₁₆;

96699669₁₆, 96969696₁₆, 99669966₁₆, 99999999₁₆;

a55aa55a₁₆, a5a5a5a5₁₆, aa55aa55₁₆, aaaaaaaa₁₆;

c33cc33c₁₆, c3c3c3c3₁₆, cc33 cc33₁₆, cccccccc₁₆;

f00ff00f₁₆, f0f0f0f0₁₆, ff00ff00₁₆, ffffffff₁₆, for modifying the error detection bits.

15. The method of claim 10, wherein the data block further comprising at least a third field having a third plurality of bits, and the method further comprising the steps of:

decoding the third plurality of bits to generate second decoding results;

selecting a second error injection mask based on the second decoding results;

further modifying the first plurality of bits with the second error injection mask to generate the modified first plurality of bits that includes the resultant error detection value; and

further detecting whether the second decoding results for the third field are correct based on the resultant error detection value indicated in the first field.

16. A device for error detection in a data block, comprising:

a processing device;

generating a data block comprising a first field having a first plurality of bits that includes an error detection portion indicating an error detection value based on a first portion of the first plurality of bits and used for error detection in decoding the first portion of the first plurality of bits, and the data block further comprising at least a second field having a second plurality of bits;

selecting an error injection mask based on the second plurality of bits; and

modifying the first plurality of bits with the error injection mask to generate a modified first plurality of bits that is used for error detection in decoding the second plurality of bits; and

a transmitter transmitting the data block with the modified first plurality of bits.

17. The device of claim 16, wherein the device comprises one of a mobile station and a base station.

18. The device of claim 16 further comprising:

a receiver receiving a second data block comprising a third field having a third plurality of bits that includes an error detection portion indicating an error detection value, the second data block further comprising at least a fourth field having a fourth plurality of bits;

decoding the fourth plurality of bits to generate decoding results;

selecting a second error injection mask based on the decoding results;

modifying the third plurality of bits using the second error injection mask to generate a modified third plurality of bits that includes a resultant error detection value; and

detecting whether the decoding results for the fourth field are correct based on the resultant error detection value indicated in the third field.

19. The device of claim 16, wherein the device operates in accordance with ETSI (European Telecommunications Standards Institute) TS (Technical Specification) 102 361-1.

20. The device of claim 16, wherein the data block further comprising at least a third field having a third plurality of bits, and the processing device further:

selecting a second error injection mask based on the third plurality of bits; and

further modifying the first plurality of bits with the second error injection mask to generate the modified first plurality of bits that is further used for error detection in decoding the third plurality of bits.