Method and system for hierarchical hardware mapping for software design

• US 20080052665A1
• Filed: 08/22/2007
• Published: 02/28/2008
• Est. Priority Date: 08/22/2006
• Status: Active Grant

• Current Assignee: Caterpillar Incorporated
• Original Assignee: Caterpillar Incorporated
• Inventors: Bray, Steven Christopher
• Granted Patent: US 8,146,052 B2
• Time in Patent Office: Days
• US Class Current: 717/105
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

The present disclosure is directed toward a method for hierarchical hardware mapping in a software design environment. The method comprises the step of providing a software design tool on a graphical interface of a computer system. The method also includes receiving, in the software design tool, graphical representation of at least a portion of software and receiving, in the software design tool, graphical representation of at least a portion of hardware. The method may further include receiving, in the software design tool, one or more bindings between software and hardware, wherein the one or more bindings form a set of bindings, and storing the set of bindings for use in one or more software designs.

Claims

1. A method for hierarchical hardware mapping in a software design environment comprising:

providing a software design tool on a graphical interface of a computer system;

receiving, in the software design tool, graphical representation of at least a portion of software;

receiving, in the software design tool, graphical representation of at least a portion of hardware;

receiving, in the software design tool, one or more bindings between software and hardware, wherein the one or more bindings form a set of bindings; and

storing the set of bindings for use in one or more software designs.

2. The method of claim 1, further including generating at least a portion of software code associated with the one or more bindings between software and hardware.

3. The method of claim 2, wherein the at least a portion of hardware includes at least one of an electronic control unit, a processor, a virtual memory space, a memory device, or a connector pin associated with an embedded system, and wherein the set of bindings includes one or more bindings of software to the at least one of an electronic control unit, a processor, a virtual memory space, a memory device, or a connector pin associated with an embedded system.

4. The method of claim 2, further including providing the at least a portion of software code to an embedded system, wherein the portion of software code, when executed by a processor associated with the embedded system, is configured to control an operational aspect associated with one or more components associated with the embedded system.

5. The method of claim 2, wherein the stored set of bindings may be automatically incorporated within one or more system compositions based on an association between a portion of the graphical representation of the at least a portion of software and the stored set of bindings.

6. The method of claim 1, wherein the set of bindings includes a plurality of sublevels, whereby one set of bindings may include one or more other sets of bindings.

7. The method of claim 1, further including receiving, by the software design tool, a user-defined restriction that limits a portion of the software to a particular thread of execution, virtual memory space, processor, or type or instance of electronic control unit.

8. The method of claim 7, wherein the software design tool may be configured to restrict the one or more bindings between software and hardware.

9. The method of claim 1, wherein the software corresponding to the graphical representation of at least a portion of software is configured to be simulated by the software design tool.

10. The method of claim 1, wherein the software corresponding to the graphical representation of at least a portion of software is defined by a hierarchy of function block diagrams.

11. The method of claim 1, wherein at least a portion of the graphical representations may include at least one of descriptive text, visual characteristics of the hardware, or symbolic indication of characteristics associated with the software.

12. A computer-readable medium for use on a computer system, the computer-readable medium including computer-executable instructions for performing the method of claim 1.

13. A computer system comprising:

a display;

a processor configured to;

provide a software design tool on a graphical interface of a computer system;

receive, in the software design tool, graphical representation of at least a portion of software;

receive, in the software design tool, graphical representation of at least a portion of hardware;

receive, in the software design tool, one or more bindings between software and hardware, wherein the one or more bindings form a set of bindings; and

store the set of bindings for use in one or more software designs.

14. The computer system of claim 13, further including generating at least a portion of software code associated with the one or more bindings between software and hardware.

15. The computer system of claim 14, wherein the at least a portion of hardware includes at least one of an electronic control unit, a processor, a virtual memory space, a memory device, or a connector pin associated with an embedded system, and wherein the set of bindings includes one or more bindings of software to the at least one of an electronic control unit, a processor, a virtual memory space, a memory device, or a connector pin associated with an embedded system.

16. The computer system of claim 14, further including providing the at least a portion of software code to an embedded system, wherein the portion of software code, when executed by a processor associated with the embedded system, is configured to control an operational aspect associated with one or more components associated with the embedded system.

17. The computer system of claim 14, wherein the stored set of bindings may be automatically incorporated within one or more system compositions based on an association between a portion of the graphical representation of the at least a portion of software and the stored set of bindings.

18. The computer system of claim 13, wherein the set of bindings includes a plurality of sublevels, whereby one set of bindings may include one or more other sets of bindings.

19. The computer system of claim 13, further including receiving, by the software design tool, a user-defined restriction that limits a portion of the software to a particular thread of execution, virtual memory space, processor, or type or instance of electronic control unit.

20. The computer system of claim 19, wherein the software design tool may be configured to restrict the one or more bindings between software and hardware.

21. The computer system of claim 13, wherein the software corresponding to the graphical representation of at least a portion of software is configured to be simulated by the software design tool.

22. The computer system of claim 13, wherein the software corresponding to the graphical representation of at least a portion of software is defined by a hierarchy of function block diagrams.

23. The computer system of claim 13, wherein at least a portion of the graphical representations may include at least one of descriptive text, visual characteristics of the hardware, or symbolic indication of characteristics associated with the software.

24. A method for mapping a software hierarchy to hardware in a software design environment comprising:

providing a software design tool on a graphical interface of a computer system;

receiving, in the software design tool, graphical representation of at least a portion of software;

receiving, in the software design tool, a user-defined designation associating a level of the software hierarchy with a hardware device; and

storing the user-defined designation for use in one or more software designs.

25. The method of claim 24, wherein the user-defined designation includes at least one of a numeric, alphabetic, or alphanumeric identifier associated with the hardware device.

26. The method of claim 25, wherein the software design tool is configured, if the hardware device is first added to the design, to provide a notification to a user of the computer system that association between the hardware device and a level of the software hierarchy is required.

27. The method of claim 24, wherein the user-defined designation includes at least one of a numeric, alphabetic, or alphanumeric identifier associated with the level of the software hierarchy.

28. The method of claim 24, wherein the software design tool maintains a list of user-defined designations and a software hierarchy corresponding to each of the user-defined designations.

29. The method of claim 28, wherein the software design tool is configured, if the level of the software hierarchy is first defined within the design, to provide a notification to a user of the computer system that association between the level of the software hierarchy and a hardware device is required.