Fabricating method for printed circuit board

• US 20080052905A1
• Filed: 09/05/2007
• Published: 03/06/2008
• Est. Priority Date: 09/06/2006
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Kim, Joon-Sung, Yoo, Je-Gwang, Watanabe, Ryoichi, Min, Byoung-Youl, Kim, Seung-Chul, Kang, Myung-San
• Granted Patent: US 8,065,797 B2
• Time in Patent Office: Days
• US Class Current: 29/846
• CPC Class Codes: H05K 2201/0361 Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
• CPC Class Codes: H05K 2201/0376 Flush conductors, i.e. flush with the surface of the printed circuit
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 2203/0278 Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
• CPC Class Codes: H05K 2203/0384 Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
• CPC Class Codes: H05K 2203/0582 Coating by resist, i.e. resist used as mask for application of insulating coating or of second resist
• CPC Class Codes: H05K 2203/1152 Replicating the surface structure of a sacrificial layer, e.g. for roughening
• CPC Class Codes: H05K 2203/1189 Pressing leads, bumps or a die through an insulating layer
• CPC Class Codes: H05K 2203/308 Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
• CPC Class Codes: H05K 3/0014 Shaping of the substrate, e.g. by moulding
• CPC Class Codes: H05K 3/0017 Etching of the substrate by chemical or physical means
• CPC Class Codes: H05K 3/045 by making a conductive layer having a relief pattern, followed by abrading of the raised portions
• CPC Class Codes: H05K 3/06 the conductive material being removed chemically or electrolytically, e.g. by photo-etch process semi-additive methods H05K3/108
• CPC Class Codes: H05K 3/107 by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/20 by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/205 using a pattern electroplated or electroformed on a metallic carrier
• CPC Class Codes: H05K 3/426 initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/4614 the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/465 by applying an insulating layer having channels for the next circuit layer
• CPC Class Codes: H05K 3/4658 : characterized by laminating a prefabricated metal foil pattern, e.g. by transfer
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49156 : with selective destruction of conductive paths
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

A method of fabricating a printed circuit board is disclosed. A method of fabricating a printed circuit board that includes: stacking an insulation layer on at least one surface of a core layer, on which an inner circuit is formed, and forming an outer circuit pattern; burying the outer circuit pattern in the insulation layer; removing the outer circuit pattern to form minute grooves and curing the insulation layer; and forming an outer circuit by filling metal in the minute grooves, makes it possible to readily form high-resolution fine-line circuits, as well as to reduce fabrication costs and increase productivity.

Claims

1. A method of fabricating a printed circuit board, the method comprising:

stacking an insulation layer on at least one surface of a core layer and forming an outer circuit pattern, the core layer having an inner circuit formed thereon;

burying the outer circuit pattern in the insulation layer;

removing the outer circuit pattern to form minute grooves and curing the insulation layer; and

forming an outer circuit by filling metal in the minute grooves.

2. The method of claim 1, further comprising electrically connecting the outer circuit and the inner circuit.

3. The method of claim 1, wherein the outer circuit pattern is formed on the insulation layer by performing lithography with photoresist.

4. The method of claim 1, wherein the outer circuit pattern is formed on a carrier by performing lithography with photoresist.

5. The method of claim 1, wherein the insulation layer is made of a thermosetting resin, and the insulation layer is in an uncured state during the burying.

6. The method of claim 1, wherein the insulation layer is made of a thermoplastic resin, and the outer circuit pattern is transcribed into the insulation layer while the insulation layer is heated to a temperature above a transition temperature, during the burying.

7. The method of claim 1, wherein the outer circuit pattern is transcribed into the insulation layer by pressing the outer circuit pattern with a pressing plate having a flat surface.

8. The method of claim 1, wherein the outer circuit pattern is removed by dissolving or swelling.

9. The method of claim 1, wherein forming the outer circuit comprises, after filling the minute grooves using copper plating to form the outer circuit, performing a planarization operation.

10. The method of claim 2, wherein the electrically connecting comprises, after removing the outer circuit pattern, forming a via hole such that exposes a portion of the inner circuit and forming a plating layer on an inner perimeter of the via hole.

11. The method of claim 1, wherein at least one bump is formed on the outer circuit pattern, the bump transcribed during the burying to be in contact with the inner circuit and then removed such that a hole is formed, and a plating layer is formed in an inner perimeter of the hole such that the inner circuit and the outer circuit are electrically connected.

12. A method of fabricating a printed circuit board, the method comprising:

preparing a core layer having an inner circuit formed thereon;

pressing at least one carrier having an outer circuit and at least one bump formed thereon onto an insulation layer with the insulation layer interposed on at least one side of the core layer, such that the outer circuit and the bump are inserted in the insulation layer, the bump inserted in the insulation layer to be in contact with the inner circuit and the outer circuit; and

electrically connecting the inner circuit with the outer circuit after removing the carrier and the bump.

13. The method of claim 12, wherein the bump is formed in a metal plate, having three different types of a first metal layer, a second metal layer, and a third metal layer stacked sequentially, by selectively removing the first metal layer, and

the outer circuit is electrically connected with the bump.

14. The method of claim 13, wherein electrically connecting the inner circuit with the outer circuit after removing the carrier and the bump comprises removing a portion of the second metal layer to expose a portion of the bump and then removing the bump by etching.

15. The method of claim 14, wherein the inner circuit and the outer circuit are electrically connected by removing the bump and then filling the inside by plating.

16. The method of claim 15, wherein a planarization operation is performed after the plating.

17. A method of fabricating a printed circuit board, the method comprising:

forming at least one bump on a carrier using a soluble polymer;

burying a via in an insulation member and then removing the carrier and dissolving the bump to form a through-hole; and

forming an upper circuit and a lower circuit on either side of the insulation member and forming a via hole using the through-hole, the via hole electrically connecting the upper circuit and lower circuit.

18. The method of claim 17, wherein the bump is formed by a water-soluble polymer, and the bump is removed by water-cleansing.