Method, apparatus and system to reduce readout delay in a sensor

• US 20080054164A1
• Filed: 08/31/2006
• Published: 03/06/2008
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Johansson, Robert
• Granted Patent: US 7,732,748 B2
• Time in Patent Office: Days
• US Class Current: 250/214R
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

Methods, devices, and systems for improving (i.e., reducing) the settling time of an output signal read from a photo sensor and improving the PSRR of the supply voltage are disclosed, wherein a detected charge in a pixel is converted to a voltage and drives a source follower transistor. A bias transistor is coupled in series with the source follower transistor and includes an output therebetween. The bias transistor is driven to source a reduced current when the voltage results from a readout of a reset value of the pixel and the bias transistor is driven to source an enhanced current when the voltage results from a readout of a sensed signal value.

Claims

1. A method of reading out a signal to an output from a pixel in an active pixel sensor (APS), comprising:

converting a detected charge in the pixel into a voltage;

driving a source follower transistor in response to the voltage;

driving a bias transistor to source a reduced current when the voltage results from a readout of a reset value of the pixel; and

driving the bias transistor to source an enhanced current when the voltage results from a readout of a sensed signal value, the bias transistor coupled in series with the source follower transistor and having the output therebetween.

2. The method of claim 1, further comprising:

generating a reference current;

enhancing sourcing of the bias transistor in response to the reference current when the voltage results from the readout of a reset value; and

reducing sourcing of the bias transistor to source the reference current when the voltage results from the readout of a sensed signal value.

3. The method of claim 2, further comprising current mirroring a first current resulting from driving the source follower to determine driving the bias transistor with the reduced current of the enhanced current.

4. The method of claim 1, further comprising current mirroring the reference signal with the bias transistor.

5. The method of claim 1, further comprising individually regulating a supply voltage to source to the source follower transistor in each pixel in a column of pixels.

6. The method of claim 1, further comprising additionally pulling up the output when the voltage results from the readout of a reset value.

7. A readout circuit for an active pixel sensor (APS) circuit, comprising:

a bias transistor configured for coupling in a source follower configuration with an output transistor of a pixel and having an output therebetween, the output transistor responsive to a voltage generated by a photo sensor of the pixel; and

a minimum current selector coupled to a gate of the bias transistor and configured to drive the bias transistor to source a reduced current when the voltage results from a readout of a reset value and further configured to drive the bias transistor to source an enhanced current when the voltage results from a readout of a sensed signal value of one of the plurality of pixels.

8. The readout circuit of claim 7, further comprising a reference generator coupled to the minimum current selector and configured to generate a reference current supplied to the minimum current selector to either enhance sourcing of the bias transistor in response to the reference current when the voltage results from the readout of a reset value or to reduce sourcing of the bias transistor to source the reference current when the voltage results from the readout of a sensed signal value.

9. The readout circuit of claim 7, further comprising a first current mirror coupling a first current resulting from driving the output transistor with the minimum current selector to mirror current of the first current to determine whether to drive the bias transistor with the reduced current or the enhanced current.

10. The readout circuit of claim 8, further comprising a second current mirror coupling the reference current with the bias transistor.

11. The readout circuit of claim 7, further comprising a voltage regulator coupled to a drain of an output transistor and configured to individually regulate a supply voltage to source to the output transistor of each pixel in a column of pixels.

12. The readout circuit of claim 7, further comprising a pull-up transistor coupled to the output and configured to pull-up the output when the voltage results from the readout of a reset value.

13. An active pixel sensor (APS) circuit, comprising:

a plurality of pixels in at least one column of an array, each of the plurality of pixels including a photo sensor, an output transistor and a row select transistor, the output transistor responsive to a voltage generated by the photo sensor; and

a readout circuit connected to at least one column of the plurality of pixels, the readout circuit including;

a bias transistor connected in a source follower arrangement with the output transistor and the row select transistor, the bias transistor coupled in series with the output transistor and having the output therebetween; and

a minimum current selector coupled to drive the bias transistor, the minimum current selector configured to drive the bias transistor to source a reduced current when the voltage results from a readout of a reset value and further configured to drive the bias transistor to source an enhanced current when the voltage results from a readout of a sensed signal value of one of the plurality of pixels.

14. The active pixel sensor (APS) circuit of claim 13, further comprising a reference generator configured to generate a reference current used to determine whether to enhance sourcing of the bias transistor in response to the reference current when the voltage results from the readout of a reset value or to reduce sourcing of the bias transistor at a level of the reference current when the voltage results from the readout of a sensed signal value.

15. The active pixel sensor (APS) circuit of claim 14, further comprising a first current mirror configured to mirror current of a first current resulting from driving the output transistor to determine whether to drive the bias transistor with the reduced current or the enhanced current.

16. The active pixel sensor (APS) circuit of claim 13, further comprising a second current mirror configured to mirror current of the reference signal with the bias transistor.

17. The active pixel sensor (APS) circuit of claim 13, further comprising a voltage regulator configured to individually regulate a supply voltage to source to the output transistor in each column of pixels in the active pixel sensor (APS) circuit.

18. The active pixel sensor (APS) circuit of claim 13, further comprising a pull-up transistor configured to pull-up the output when the voltage results from the readout of a reset value.

19. An imaging device, comprising:

an active pixel sensor (APS) circuit including a plurality of pixels arranged in a plurality of rows and a plurality of columns, the active pixel sensor (APS) circuit including a readout circuit connected to each of the plurality of columns of the plurality of pixels and further configured to generate an output signal representative of a signal stored in one of the plurality of pixels wherein the readout circuit is driven to source the output signal from a reduced current when a reset value is read from one of the plurality of pixels and the readout circuit is driven to source the output signal from an enhanced current when a sensed signal value is read from one of the plurality of pixels;

a row decoder operably coupled to the active pixel sensor (APS) circuit and configured for selecting each row of the plurality of rows; and

a column decoder operably coupled to the active pixel sensor (APS) circuit and configured for receiving in parallel, at least one signal from each pixel of a selected row.

20. The imaging device of claim 19, wherein

each of the plurality of pixels includes a photo sensor, an output transistor and a row select transistor, the output transistor responsive to a voltage generated by the photo sensor, and

the readout circuit includes a bias transistor connected in a source follower arrangement with the output transistor and the row select transistor, the bias transistor coupled in series with the output transistor and having an output therebetween for generating the output signal thereon.

21. The imaging device of claim 20, further comprising a minimum current selector coupled to drive the bias transistor, the minimum current selector configured to drive the bias transistor to source the reduced current when the voltage results from a readout of the reset value and further configured to drive the bias transistor to source the enhanced current when the voltage results from a readout of the sensed signal value of one of the plurality of pixels.

22. The imaging device of claim 21, further comprising a reference generator coupled to the minimum current selector and configured to generate a reference current supplied to the minimum current selector to either enhance sourcing of the bias transistor in response to the reference current when the voltage results from the readout of a reset value or to reduce sourcing of the bias transistor to source the reference current when the voltage results from the readout of a sensed signal value.

23. The imaging device of claim 21, further comprising a voltage regulator configured to couple to a drain of an output transistor to individually regulate a supply voltage to source to the output transistor to each pixel in a column of pixels.

24. The imaging device of claim 21, further comprising a pull-up transistor coupled to the output and configured to pull-up the output when the voltage results from the readout of a reset value.

25. The imaging device of claim 19, further comprising an analog-to-digital converter coupled to the active pixel sensor (APS) circuit and configured to convert the output signal into a digital value.

26. The imaging device of claim 25, further comprising a memory configured for storing the digital value representative of the sensed signal value.

27. An electronic system, comprising:

a processor-based device; and

an imaging device coupled to the processor-based device, the imaging device configured to read out a signal to an output from a pixel in an active pixel sensor (APS) circuit, the imaging device including a source follower circuit comprised of a source follower transistor and a bias transistor wherein a detected charge in the pixel drives the source follower transistor and the bias transistor is either driven to source a reduced current when the voltage results from a readout of a reset value of the pixel or driven to source an enhanced current when the voltage results from a readout of a sensed signal value, the bias transistor and the source follower transistor include the output therebetween.

28. The electronic system of claim 27, further comprising a reference generator configured to generate a reference current for enhancing and reducing sourcing of the bias transistor in response to the voltage.

29. The electronic system of claim 27, further comprising a voltage regulator configured to individually regulate a supply voltage to source to the source follower transistor in each column of pixels in the active pixel sensor (APS) circuit.

30. The electronic system of claim 27, further comprising a pull-up transistor coupled to the output and configured to pull-up the output when the voltage results from the readout of a reset value.