Semiconductor Device and Manufacturing Method Thereof

• US 20080054333A1
• Filed: 08/29/2007
• Published: 03/06/2008
• Est. Priority Date: 08/29/2006
• Status: Active Grant

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: KIM, SUNG JIN
• Granted Patent: US 7,763,930 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Provided are a semiconductor device and a manufacturing method thereof. A pair of adjacent gate structure can be formed on a substrate. Mask patterns exposing a portion located between the gate structures are formed. The substrate portion located between the gate structures can be etched using the mask patterns as an etch mask to form a pocket. First conduction type impurities can be implanted into the pocket to form a first impurity layer in a surface of the pocket. Second conduction type impurities can be implanted into the pocket to form a second impurity layer on the first impurity layer. The pocket can be filled with an insulating material. Accordingly, impurities having a type opposite to the type of source junction impurities are implanted into the pocket to reduce a potential barrier of a source junction. Consequently, punch-through generated between a source and a drain can be inhibited.

Claims

1. A semiconductor device, comprising:

a pair of adjacent gate structures disposed on a substrate;

a pocket formed in a common source region between the gate structures;

a first conduction type impurity layer in a surface of the pocket;

a second conduction type impurity layer formed in a surface of the first conduction type impurity layer; and

an insulating material filling the pocket.

2. The semiconductor device according to claim 1, wherein the first conduction type impurity layer comprises BF⁺ ions, and the second conduction type impurity layer comprises As⁺ ions.

3. The semiconductor device according to claim 1, wherein the number of first conduction type impurity ions in the first conduction type impurity layer is in a range of 4×

10¹⁵-6×

10¹⁶ atoms/cm² implanted with an ion implanting energy is in a range of 40-60 KeV, and wherein the number of second conduction type impurity ions in the second conduction type impurity layer is in a range of 1×

10¹⁵-3×

10¹⁵ atoms/cm², implanted with ion implanting energy in a range of 10-30 KeV.

4. The semiconductor device according to claim 1, wherein the gate structures comprise gate electrodes having a stacked structure of a tunnel oxide layer pattern, a floating gate, an ONO layer pattern, and a control gate.

5. The semiconductor device according to claim 4, wherein the floating gate and the control gate comprise polysilicon.

6. A method for manufacturing a semiconductor device, the method comprising:

forming a pair of adjacent gate structures on a substrate;

forming mask patterns exposing a portion of the substrate located between the gate structures;

etching the portion of the substrate located between the gate structures using the mask patterns as an etch mask to form a pocket;

implanting first conduction type impurities into the pocket to form a first conduction type impurity layer in a surface of the pocket;

implanting second conduction type impurities into the pocket to form a second conduction type impurity layer on the first conduction type impurity layer; and

filling the pocket with an insulating material.

7. The method according to claim 6, wherein the first conduction type impurities are p type impurities, and the second conduction type impurities are n type impurities.

8. The method according to claim 7, wherein the first conduction type impurities comprise BF⁺ ions.

9. The method according to claim 7, wherein the second conduction type impurities comprise As⁺ ions.

10. The method according to claim 6, wherein the first conduction type impurities are implanted into the pocket in a direction perpendicular to the substrate, and the second conduction type impurities are implanted into the pocket in a direction inclined with respect to the substrate.

11. The method according to claim 6, wherein the first conduction type impurities are implanted in a range of 4×

10¹⁵-6×

10¹⁶ atoms/cm², at an ion implanting energy in a range of 40-60 KeV, and the second conduction type impurities are implanted in a range of 1×

10¹⁵-3×

10¹⁵ atoms/cm² at an ion implanting energy in a range of 10-30 KeV.

12. The method according to claim 6, further comprising, after forming the first conduction type impurity layer, performing an annealing process to recover a damage of the substrate and thermally diffuse the first conduction type impurities.

13. The method according to claim 6, wherein forming the pair of the adjacent gate structures comprises:

forming a tunnel oxide layer on the substrate, a floating gate layer on the tunnel oxide layer, an ONO layer on the floating gate layer, and a control gate layer on the ONO layer;

forming a photoresist pattern on the control gate layer;

sequentially etching the tunnel oxide layer, the floating gate layer, the ONO layer, and the control gate layer using the photoresist pattern as an etch mask to form the gate structures including a tunnel oxide layer pattern, a floating gate, an ONO pattern, and a control gate.

14. The method according to claim 13, wherein the mask pattern exposes at least portions of upper surfaces of the gate structures.