Small-Pitch Three-Dimensional Mask-Programmable Memory

• US 20080054372A1
• Filed: 11/06/2007
• Published: 03/06/2008
• Est. Priority Date: 04/04/2004
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: ZHANG, Guobiao
• Granted Patent: US 7,728,391 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/62 Protecting access to data via a platform, e.g. using keys or access control rules
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

The present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). It is an ultra-low-cost and ultra-high-density semiconductor memory. SP-3DmM comprises a mask-programmable memory level stacked above the substrate. This memory level comprises diodes but no transistors or antifuses. Its minimum line pitch is smaller than the minimum gate pitch of the substrate transistors.

Claims

1. A small-pitch three-dimensional mask-programmable memory (SP-3DmM), comprising:

a substrate having a plurality of functional transistors; and

at least one mask-programmable memory level stacked above said substrate and coupled to selected ones of said functional transistors through a plurality of inter-level vias, said mask-programmable memory level comprising a plurality of diodes but no functional transistors;

wherein the minimum line pitch of said mask-programmable memory level is smaller than the minimum gate pitch of said functional transistors.

2. The SP-3DmM according to claim 1, wherein said mask-programmable memory level requires no electrical programming.

3. The SP-3DmM according to claim 2, wherein said mask-programmable memory level comprises no antifuse.

4. The SP-3DmM according to claim 1, wherein said substrate comprises a peripheral circuit of said mask-programmable memory level.

5. The SP-3DmM according to claim 1, wherein said substrate comprises a transistor-based memory and the minimum line pitch of said mask-programmable memory level is smaller than the minimum line pitch of said transistor-based memory.

6. The SP-3DmM according to claim 5, wherein said transistor-based memory is an embedded RAM and functions as a cache for said mask-programmable memory level.

7. The SP-3DmM according to claim 5, wherein said transistor-based memory is an embedded ROM and stores correctional data or upgrade code for said mask-programmable memory level.

8. The SP-3DmM according to claim 5, wherein the minimum line pitch of said mask-programmable memory level is smaller than the minimum line pitch of the contemporary transistor-based memory.

9. The SP-3DmM according to claim 1, wherein said diodes are natural-junction diodes.

10. The SP-3DmM according to claim 1, wherein said diodes are pillar-shaped diodes.

11. The SP-3DmM according to claim 1, wherein said diodes has a higher resistance when the current flows in one direction than the other.

12. The SP-3DmM according to claim 11, wherein said diodes are Schottky diodes.

13. The SP-3DmM according to claim 11, wherein said diodes are p-n diodes.

14. The SP-3DmM according to claim 11, wherein said diodes are p-i-n diodes.

15. The SP-3DmM according to claim 1, further comprising at least two mask-programmable memory levels.

16. The SP-3DmM according to claim 15, wherein adjacent mask-programmable memory levels share a level of address-selection lines.

17. The SP-3DmM according to claim 15, wherein adjacent mask-programmable memory levels are separated by an inter-level dielectric.

18. The SP-3DmM according to claim 1, wherein the minimum via pitch of said inter-level vias is larger than the minimum line pitch of said mask-programmable memory level.

19. The SP-3DmM according to claim 18, wherein selected ones of said inter-level vias are interleaved with respect to each other.

20. The SP-3DmM according to claim 18, wherein selected ones of said inter-level vias are displaced with respect to each other.