Power electronic package having two substrates with multiple electronic components

• US 20080054425A1
• Filed: 08/29/2006
• Published: 03/06/2008
• Est. Priority Date: 08/29/2006
• Status: Active Grant

• Current Assignee: DENSO Corporation, University of Cambridge, University of Sheffield
• Original Assignee: DENSO Corporation, University of Cambridge, University of Sheffield
• Inventors: Malhan, Rajesh Kumar, Johnson, C. Mark, Rashid, Jeremy
• Granted Patent: US 7,557,434 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 24/01 Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/33 of a plurality of layer connectors
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and a plurality of electronic components mounted on each of the substrates. The substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions. The mechanical separation provides a net axially-directed compressive force in the electronic components.

Claims

1. A power electronic package comprising:

first and second high thermal conductivity insulating non-planar substrates; and

a plurality of electronic components mounted on each of the first and second high thermal conductivity insulating non-planar substrates, wherein

the first and second high thermal conductivity insulating non-planar substrates are coupled each other at a plurality of bonding regions so that mechanical separation between the first and second high thermal conductivity insulating non-planar substrates is controlled by the number of the bonding regions, an arrangement of the bonding regions, a shape of each bonding region, and a material of the bonding regions, and

the mechanical separation provides a net axially-directed compressive force in the electronic components.

2. The package according to claim 1, wherein

the bonding regions are arranged in the arrangement in such a manner that a net residual compressive stress in the electronic components is reduced.

3. The package according to claim 1, wherein

the mechanical separation of the high thermal conductivity insulating non-planar substrates is controlled by a plurality of regions made of a material having high thermal expansion coefficient so that the net axially-directed compressive force is generated in the electronic components.

4. The package according to claim 1, wherein

the electronic components include a semiconductor transistor chip,

the semiconductor transistor chip includes a first main electrode on a first principal surface of the chip and a second main electrode on a second principal surface of the chip, and

the second principal surface is opposite to the first principal surface.

5. The package according to claim 1, wherein

the electronic components include a semiconductor diode chip,

the semiconductor diode chip includes a first main electrode on a first principal surface of the chip and a second main electrode on a second principal surface of the chip, and

the second principal surface is opposite to the first principal surface.

6. The package according to claim 1, wherein

each of the first and second high thermal conductivity insulating non-planar substrates is an electrically isolated and thermally conductive step type substrate, and

the electrically isolated and thermally conductive step type substrate includes first and second exterior surfaces for bonding electrodes of the electronic components and for providing a plurality of external buses for a two-sided electrical connection.

7. The package according to claim 6, wherein

the electrodes of the electronic components include a first main electrode,

the external buses include a first external bus electrode, and

the first external bus electrode connects to the first main electrode.

8. The package according to claim 7, wherein

the electrodes of the electronic components further include a second main electrode,

the external buses further include a second external bus electrode, and

the second external bus electrode connects to the second main electrode.

9. The package according to claim 6, wherein

the electronic components are sandwiched between the first exterior surfaces of the first and second high thermal conductivity insulating non-planar substrates.

10. The package according to claim 1, wherein

the bonding regions include electrically inactive bonding regions, and

the mechanical separation of the first and second high thermal conductivity insulating non-planar substrates is controlled by the number of the electrically inactive bonding regions, an arrangement of the electrically inactive bonding regions, and a shape of each inactive bonding region.

11. The package according to claim 1, wherein

each of the high thermal conductivity insulating non-planar substrates includes a non-bonding region, and

the non-bonding region has a height, which is small than a height of the bonding regions.

12. The package according to claim 10, wherein

the electrically inactive bonding regions are capable of bonding with a solderable electrically conductive material.

13. The package according to claim 6, wherein

the electrodes of the electronic components are capable of bonding the external buses with a solderable electrically conductive material, respectively, and

each external bus is patterned to be an external bus electrode.

14. The package according to claim 13, wherein

the high thermal conductivity insulating non-planar substrates are connected at a sandwich portion through an insulating resin,

the insulating resin is made of epoxy resin or silicone resin,

the insulating resin covers the electronic components and provides electrical isolation between the external bus electrodes.

15. The package according to claim 1, wherein

each high thermal conductivity insulating non-planar substrate includes a non-conductive ceramic substrate and a highly conductive metal member, and

the highly conductive metal members of the high thermal conductivity insulating non-planar substrates are coupled with a direct bonding copper, a direct bonding aluminum or an active metal brazing solder material.

16. The package according to claim 15, wherein

the non-conductive ceramic substrate is made of two materials, one of which is alumina, aluminum nitride, silicon nitride, silicon carbide, or diamond, and the other one of which is copper or aluminum.

17. The package according to claim 1, wherein

each high thermal conductivity insulating non-planar substrate includes copper or aluminum.

18. The package according to claim 13, wherein

each external bus electrode is disposed on each high thermal conductivity insulating non-planar substrate, and

the external bus electrode is capable of being formed by a one-bond and two-step etching method with using copper or aluminum.

19. The package according to claim 13, wherein

each external bus electrode is disposed on each high thermal conductivity insulating non-planar substrate, and

the external bus electrode is capable of being formed by a two-bond and two-step etching method with using copper or aluminum.

20. The package according to claim 1, wherein

the electronic components include a vertical type junction field effect transistor.

21. The package according to claim 1, wherein

the electronic components include a vertical type metal oxide semiconductor field effect transistor.

22. The package according to claim 1, wherein

the electronic components include a vertical type isolated gate bipolar transistor.

23. The package according to claim 1, wherein

the electronic components include a vertical type junction diode.

24. The package according to claim 1, wherein

the electronic components include a vertical type Schottky barrier diode.

25. The package according to claim 1, wherein

the electronic components include a vertical type wide band gap semiconductor transistor and a diode chip.

26. The package according to claim 1, wherein

the electronic components include a vertical type silicon carbide transistor and a diode chip.

27. The package according to claim 1, wherein

each electronic component is capable of carrying high current density.

28. The package according to claim 1, wherein

the package is formed under a process temperature, which is higher than a maximum operating temperature of the package, so that a net residual compressive stress is reduced in the electronic components.

29. The package according to claim 28, wherein

the process temperature is about 50 degree Celsius higher than the maximum operating temperature of the package.

30. The package according to claim 13, wherein

the electrodes of the electronic components and the external bus electrodes are bonded with a brazing material, which is made of Au—

Sn, Au—

Ge, or Au—

Si solder.

31. The package according to claim 30, wherein

the electrodes of the electronic components and the external bus electrodes are bonded in a single assembly step method with using a transient liquid phase bonding member, which is made of Ag—

Sn, or Ag flex.

32. The package according to claim 30, wherein

the electrodes of the electronic components and the external bus electrodes are bonded with a thermo-compressive bonding member, which is made of Au.

33. The package according to claim 1, further comprising:

a direct liquid impingement first heat exchanger unit attached to the first high thermal conductivity insulating non-planar substrate; and

a direct liquid impingement second heat exchanger unit attached to the second high thermal conductivity insulating non-planar substrate, wherein

the heat exchanger units are disposed in parallel to each other.

34. The package according to claim 33, wherein

each heat exchanger unit is made of high thermal conductivity copper- or aluminum-silicon carbide.