Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods

• US 20080054444A1
• Filed: 08/31/2006
• Published: 03/06/2008
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tuttle, Mark E.
• Granted Patent: US 7,902,643 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.

Claims

1. A microelectronic device, comprising:

a semiconductor substrate including integrated circuitry and terminals electrically coupled to the integrated circuitry;

electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals; and

a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate, wherein at least one interconnect is electrically coupled to the conductive layer.

2. The microelectronic device of claim 1 wherein the electrically conductive interconnects comprise a first interconnect and a second interconnect, and wherein the microelectronic device further comprises:

a first conductive coupler attached to the first interconnect and in electrical contact with the conductive layer at the back side of the semiconductor substrate; and

a second conductive coupler attached to the second interconnect, wherein the second conductive coupler is electrically isolated from the conductive layer.

3. The microelectronic device of claim 1 wherein:

the electrically conductive interconnects comprise a first interconnect and a second interconnect; and

the conductive backplane assembly further comprises—

a first dielectric layer on the back side of the substrate and in contact with the first and second interconnects;

a conductive layer over at least a portion of the first dielectric layer and having openings around the first and second interconnects, wherein portions of the first dielectric layer are in the openings between the conductive layer and the first and second interconnects; and

a second dielectric layer over the first dielectric layer and the conductive layer, the second dielectric layer including a first opening over the first interconnect and a second opening over the second interconnect, wherein the first opening is sized to expose a back side portion of the first interconnect, a portion of the first dielectric layer adjacent to the first interconnect, and a portion of the conductive layer adjacent to the first interconnect, and wherein the second opening is sized to expose a back side portion of the second interconnect without exposing the conductive layer adjacent to the second interconnect; and

the device further comprises (a) a first conductive coupler in the first opening and in contact with the first interconnect and the exposed portion of the conductive layer adjacent to the first interconnect, and (b) a second conductive coupler in the second opening and in contact with the second interconnect, wherein the second conductive coupler is electrically isolated from the conductive layer.

4. The microelectronic device of claim 3 wherein:

the first dielectric layer comprises a low temperature CVD oxide;

the conductive layer comprises Al, Cu, Ni, W, and/or a conductive polymer; and

the second dielectric layer comprises a low temperature CVD oxide and/or a photosensitive polyimide.

5. The microelectronic device of claim 1 wherein:

the electrically conductive interconnects comprise a first interconnect and a second interconnect;

the conductive layer on the back side of the substrate has openings around the first and second interconnects, and wherein the conductive backplane assembly further comprises—

a dielectric layer over the conductive layer, the dielectric layer including a first opening over the first interconnect and a second opening over the second interconnect, wherein the first opening is sized to expose a back side portion of the first interconnect and a portion of the conductive layer adjacent to the first interconnect, and wherein the second opening is sized to expose a back side portion of the second interconnect without exposing the conductive layer; and

the device further comprises (a) a first conductive coupler in the first opening and in contact with the first interconnect and the exposed portion of the conductive layer adjacent to the first interconnect, and (b) a second conductive coupler in the second opening and in contact with the second interconnect, wherein the second conductive coupler is electrically isolated from the conductive layer.

6. The microelectronic device of claim 5 wherein:

the conductive layer comprises an argon pre-sputter, at least one of a titanium layer and a tantalum layer, and an aluminum layer; and

the dielectric layer comprises a low temperature CVD oxide and/or a photosensitive polyimide.

7. The microelectronic device of claim 1 wherein:

the electrically conductive interconnects comprise a first interconnect and a second interconnect; and

the conductive layer on the back side of the substrate has a first opening around the first interconnect and the conductive layer directly contacts an end of the second interconnect, and wherein the conductive backplane assembly further comprises—

a dielectric layer over the conductive layer, the dielectric layer including a first opening over the first interconnect to expose a back side portion of the first interconnect, and a second opening aligned with the second interconnect to expose the conductive layer over a back side portion of the second interconnect; and

the device further comprises (a) a first conductive coupler in the first opening and in contact with the first interconnect, wherein the first conductive coupler is electrically isolated from the conductive layer, and (b) a second conductive coupler in the second opening and in direct contact with the conductive layer.

8. The microelectronic device of claim 7 wherein:

the conductive layer comprises Al, Cu, Ni, W, and/or a conductive polymer; and

the dielectric layer comprises a low temperature CVD oxide and/or a photosensitive polyimide.

9. A microfeature workpiece, comprising:

a semiconductor substrate having a front side, a back side, and a plurality of microelectronic dies on and/or in the substrate, the individual dies including integrated circuitry and bond-pads electrically coupled to the integrated circuitry;

a plurality of electrically conductive through-substrate interconnects electrically coupled to corresponding terminals; and

a shield layer at the back side of the semiconductor substrate, wherein first interconnects of individual dies are electrically coupled to the shield layer, and second interconnects of individual dies are electrically isolated from the shield layer.

10. The microfeature workpiece of claim 9 wherein the shield layer includes a conductive layer that provides electromagnetic interference (EMI) shielding and grounding for the individual dies.

11. The microfeature workpiece of claim 9 wherein:

the individual first and second interconnects have a first portion coupled to corresponding bond-pads at the front side of the substrate and a second portion at the back side of the substrate; and

the microfeature workpiece further comprises (a) first conductive couplers attached to the second portions of the first interconnects and in electrical contact with the shield layer, and (b) second conductive couplers attached to the second portions of the second interconnects and electrically isolated from the shield layer.

12. A microelectronic device, comprising:

a semiconductor substrate including a front side, a back side opposite the front side, integrated circuitry, and an array of bond-pads at the front side electrically coupled to the integrated circuitry;

a plurality of electrically conductive interconnects extending through the substrate, the interconnects having first portions electrically coupled with corresponding bond-pads and second portions at the back side;

a metal layer at the back side of the semiconductor substrate having an array of openings aligned with corresponding interconnects, wherein the second portion of at least one of the interconnects is received in a corresponding opening;

a dielectric layer over the metal layer, the dielectric layer having openings aligned with the interconnects; and

a plurality of solder balls attached to corresponding interconnects at the back side of the semiconductor substrate, wherein at least one of the solder balls is configured to electrically couple the integrated circuitry to the metal layer within the footprint of the semiconductor substrate and at least one solder ball is electrically isolated from the metal layer.

13. The microelectronic device of claim 12 wherein the metal layer comprises at least one of Al, Cu, Ni, and W deposited over a layer of at least one of titanium and tantalum.

14. The microelectronic device of claim 12 wherein the plurality of electrically conductive interconnects comprises a first interconnect and a second interconnect and the dielectric layer comprises a second dielectric layer, and wherein

the microelectronic device further comprises a first dielectric layer on the back side of the substrate and in contact with the first and second interconnects, wherein the first dielectric layer isolates the metal layer from direct contact with the substrate and the first and second interconnects;

the second dielectric layer includes a first opening having a first cross-sectional dimension over the first interconnect and a second opening having a second cross-sectional dimension less than the first cross-sectional dimension over the second interconnect, wherein the first opening is sized to expose the second portion of the first interconnect and a portion of the metal layer adjacent to the first interconnect, and wherein the second opening is sized to expose only the second portion of the second interconnect, and

the plurality of solder balls attached to corresponding interconnects at the back side of the semiconductor substrate comprises (a) a first solder ball in the first opening and in contact with the first interconnect and the adjacent portion of the metal layer, and (b) a second solder ball in the second opening and in contact with the second interconnect, wherein the second solder ball is electrically isolated from the metal layer.

15. The microelectronic device of claim 12 wherein the plurality of electrically conductive interconnects comprises a first interconnect and a second interconnect, and wherein:

the dielectric layer includes a first opening having a first cross-sectional dimension over the first interconnect and a second opening having a second cross-sectional dimension less than the first cross-sectional dimension over the second interconnect, wherein the first opening is sized to expose the second portion of the first interconnect and a portion of the metal layer adjacent to the first interconnect, and wherein the second opening is sized to expose only the second portion of the second interconnect, and

the plurality of solder balls attached to corresponding interconnects at the back side of the semiconductor substrate comprises (a) a first solder ball in the first opening and in contact with the first interconnect and the adjacent portion of the metal layer, and (b) a second solder ball in the second opening and in contact with the second interconnect, wherein the second solder ball is electrically isolated from the metal layer.

16. A microelectronic device, comprising:

a semiconductor substrate including integrated circuitry and bond-pads electrically coupled to the integrated circuitry;

electrically conductive through-substrate interconnects in contact with corresponding bond-pads and having back side portions; and

an EMI shield at a back side of the semiconductor substrate for EMI shielding, wherein the back side portion of at least one interconnect is electrically coupled to the EMI shield, and the back side portion of at least one other interconnect is electrically isolated from the EMI shield.

17. The microelectronic device of claim 16, further comprising a plurality of conductive couplers attached to corresponding interconnects at the back side of the semiconductor substrate, wherein at least one of the conductive couplers is in contact with the EMI shield and one of the conductive couplers is not.

18. The microelectronic device of claim 16 wherein the interconnects are positioned to electrically couple the integrated circuitry to the EMI shield within the footprint of the semiconductor substrate.

19. A microelectronic assembly, comprising:

a first microelectronic device having—

a first microelectronic die with a first integrated circuit and an array of first bond-pads electrically coupled to the first integrated circuit;

first electrically conductive interconnects extending at least partially through the first die and in contact with corresponding first bond-pads; and

a first conductive backplane assembly having a first conductive layer at a back side of the first die, wherein at least one first interconnect is electrically coupled to the first conductive layer; and

a second microelectronic device coupled to the first microelectronic device in a stacked configuration, the second microelectronic device having—

a second microelectronic die with a second integrated circuit and an array of second bond-pads electrically coupled to the second integrated circuit;

second electrically conductive interconnects extending at least partially through the second die and in contact with corresponding second bond-pads; and

a second conductive backplane assembly having a second conductive layer at a back side of the second die, wherein at least one second interconnect is electrically coupled to the second conductive layer.

20. The microelectronic assembly of claim 19 wherein the first device is a memory device and the second device is an imager.

21. The microelectronic assembly of claim 19 wherein the first device is a processor and the second device is an imager.

22. The microelectronic assembly of claim 19 wherein the first device is a NAND flash memory and the second device is a random access memory device.

23. The microelectronic assembly of claim 19 wherein the first device and the second device are memory devices.

24. A microelectronic device, comprising:

a semiconductor substrate including a front side, a back side opposite the front side, integrated circuitry, and an array of bond-pads at the front side of the substrate electrically coupled to the integrated circuitry;

a plurality of electrically conductive interconnects extending through the substrate, the interconnects having front side portions electrically coupled with corresponding bond-pads, and back side post portions at the back side of the substrate;

a conductive layer at the back side of the substrate having an array of openings aligned with corresponding interconnects such that the back side post portions of the interconnects extend through the openings in the conductive layer; and

dielectric spacers in the openings between the conductive layer and the back side post portions of the corresponding interconnects, wherein the back side post portions of first interconnects are electrically coupled to the conductive layer, and the back side post portions of second interconnects are electrically isolated from the conductive layer.

25. The microelectronic device of claim 24, further comprising:

a dielectric cover layer over the conductive layer and the back side post portions of the first and second interconnects, the cover layer including first openings over the first interconnects and second openings over the second interconnects, wherein the first openings are sized to expose the back side post portions of the first interconnects and a portion of the conductive layer adjacent to the first interconnects, and wherein the second openings are sized to expose only the back side post portions of the interconnects;

first conductive couplers in the first openings and in contact with the back side post portions of the first interconnects and the exposed portions of the conductive layer proximate to the corresponding first interconnects; and

second conductive couplers in the second openings and in contact with the back side post portions of the second interconnects, wherein the second conductive couplers are electrically isolated from the conductive layer.

26. A microfeature workpiece including a semiconductor substrate having a front side and a back side, the workpiece comprising:

a plurality of microelectronic dies on and/or in the semiconductor substrate, the individual dies including integrated circuitry, an array of bond-pads electrically coupled to the integrated circuitry, a plurality of electrically conductive through-substrate interconnects electrically coupled to corresponding bond-pads, and a back side metal layer, wherein at least one of the interconnects is electrically coupled to the metal layer; and

a plurality of scribe lines spacing apart the individual dies.

27. A method of processing a semiconductor substrate, the semiconductor substrate having integrated circuitry and a plurality of terminals electrically coupled to the integrated circuitry, the method comprising:

forming a plurality of electrically conductive interconnects extending at least partially through the substrate and in contact with corresponding terminals, the interconnects having back side portions at a back side of the semiconductor substrate;

constructing a conductive backplane at the back side of the semiconductor substrate; and

electrically coupling at least one of the back side portions of the interconnects to the backplane, and electrically isolating at least one other interconnect from the backplane.

28. The method of claim 27 wherein electrically coupling at least one of the interconnects to the backplane comprises placing a conductive coupler in contact with a back side portion of a particular interconnect and an adjacent portion of the backplane, and wherein electrically isolating at least one other interconnect comprises placing another conductive coupler in contact with the back side portion of the other particular interconnect and electrically isolated from the backplane.

29. The method of claim 27 wherein electrically coupling at least one of the back side portions of the interconnects to the backplane comprises electrically coupling at least one of the back side portions of the interconnects to the backplane within the footprint of the semiconductor substrate.

30. The method of claim 27 wherein:

constructing a conductive backplane at the back side of the semiconductor substrate comprises depositing a metal layer onto the back side of the substrate, the conductive layer having openings around the interconnects and dielectric spacers in the openings between the metal layer and the interconnects; and

electrically coupling at least one of the back side portions of the interconnects to the backplane comprises placing a conductive coupler one of the openings in direct contact with the corresponding interconnect and the metal layer.

31. The method of claim 27 wherein:

constructing a conductive backplane at the back side of the semiconductor substrate comprises (a) depositing a metal layer onto the back side of the substrate and electrically isolated from the interconnects, (b) depositing a dielectric layer over the metal layer, and (c) forming openings in the dielectric layer to at least partially expose the back side portions of the individual interconnects; and

electrically coupling at least one of the back side portions of the interconnects to the backplane comprises placing a solder ball in a particular opening sized to expose the corresponding interconnect and an adjacent portion of the metal layer, the solder ball being in direct contact with the respective interconnect and the metal layer.

32. The method of claim 27 wherein the plurality of electrically conductive interconnects comprises a first interconnect and a second interconnect, and wherein:

constructing a conductive backplane at the back side of the semiconductor substrate comprises—

depositing a first dielectric layer onto the back side of the substrate and in contact with the first and second interconnects;

depositing a conductive layer over the first dielectric layer;

planarizing the substrate by placing the back side of the substrate against a planarizing medium and moving the substrate and/or the planarizing medium relative to each other in a manner that removes portions of the first dielectric layer and conductive layer from the substrate to leave the remaining portions of the conductive layer out of direct contact with the first and second interconnects;

depositing a second dielectric layer over the first dielectric layer and the conductive layer; and

creating a first opening in the second dielectric layer to expose the first interconnect and a portion of the conductive layer, and creating a second opening the second dielectric layer to expose the second interconnect without exposing the conductive layer; and

electrically coupling at least one of the back side portions of the interconnects to the backplane comprises—

depositing a first conductive coupler into the first opening and in contact with the first interconnect and the conductive layer; and

depositing a second conductive coupler into the second opening and in contact with the second interconnect, wherein the second conductive coupler is out of contact with the conductive layer.

33. The method of claim 32 wherein:

depositing a first dielectric layer comprises depositing a low temperature CVD oxide;

depositing a conductive layer over the first dielectric layer comprises depositing Al, Cu, Ni, W, and/or a conductive polymer; and

depositing a second dielectric layer over the first dielectric layer and the conductive layer comprises depositing a low temperature CVD oxide and/or a photosensitive polyimide.

34. The method of claim 32 wherein the second dielectric layer comprises a low temperature CVD oxide, and wherein creating the first opening and the second opening in the second dielectric layer comprises etching the first and second openings in the second dielectric layer.

35. The method of claim 32 wherein the second dielectric layer comprises a photosensitive polyimide, and wherein creating the first opening and the second opening in the second dielectric layer comprises developing the photosensitive second dielectric layer to have the first and second openings aligned with the first and second interconnects, respectively.

36. The method of claim 27 wherein the plurality of electrically conductive interconnects comprises a first interconnect and a second interconnect, and wherein:

constructing a conductive backplane at the back side of the semiconductor substrate comprises—

depositing a conductive layer onto the back side of the substrate and over exposed back side portions of the first and second interconnects;

planarizing the substrate by placing the back side of the substrate against a planarizing medium and moving the substrate and/or the planarizing medium relative to each other in a manner that removes portions of the conductive layer from the substrate to leave the remaining portions of the conductive layer electrically isolated from the first and second interconnects;

depositing a dielectric layer over the conductive layer; and

creating a first opening in the dielectric layer to expose the first interconnect and a portion of the conductive layer, and creating a second opening the second dielectric layer to expose the second interconnect without exposing the conductive layer; and

electrically coupling at least one of the back side portions of the interconnects to the backplane comprises—

depositing a first conductive coupler into the first opening and in contact with the back side portion of the first interconnect and the conductive layer; and

depositing a second conductive coupler into the second opening and in contact with the back side portion of the second interconnect, wherein the second conductive coupler is electrically isolated from the conductive layer.

37. The method of claim 36 wherein:

depositing a conductive layer onto the back side of the substrate comprises depositing an argon pre-sputter, a barrier layer of titanium or tantalum, and a layer Al, Cu, Ni, or W over the barrier layer; and

depositing a dielectric layer over the conductive layer comprises depositing a low temperature CVD oxide and/or a photosensitive polyimide.

38. The method of claim 37 wherein the dielectric layer comprises a low temperature CVD oxide, and wherein creating the first opening and the second opening in the dielectric layer comprises etching the first and second openings in the second dielectric layer.

39. The method of claim 37 wherein the dielectric layer comprises a photosensitive polyimide, and wherein creating the first opening and the second opening in the second dielectric layer comprises developing the photosensitive second dielectric layer to have the first and second openings aligned with the first and second interconnects, respectively.

40. The method of claim 27 wherein the plurality of electrically conductive interconnects comprises a first interconnect and a second interconnect, and wherein:

constructing a conductive backplane at the back side of the semiconductor substrate comprises—

depositing a conductive layer onto the back side of the substrate and over exposed back side portions of the first and second interconnects;

applying a first layer of resist over the conductive layer and forming a first opening in the conductive layer to expose the first interconnect;

depositing a dielectric layer over the conductive layer and into the first opening over the first interconnect;

applying a second layer of resist over the dielectric layer;

exposing the first interconnect by creating a second opening in the second layer of resist and the dielectric layer, wherein the conductive layer is isolated from the second opening; and

exposing a portion of the conductive layer aligned with the second interconnect by creating a third opening in the second layer of resist and the dielectric layer; and

electrically coupling at least one of the back side portions of the interconnects to the backplane comprises—

depositing a first conductive coupler into the first opening and in contact with the first interconnect, wherein the first conductive coupler is electrically isolated from the conductive layer; and

depositing a second conductive coupler into the second opening and in direct contact with the conductive layer.

41. The method of claim 40 wherein:

depositing a conductive layer onto the back side of the substrate comprises depositing Al, Cu, Ni, W, and/or a conductive polymer; and

depositing a dielectric layer over the conductive layer comprises depositing a low temperature CVD oxide and/or a photosensitive polyimide.

42. A method of processing a semiconductor substrate having a plurality of microelectronic dies, the individual dies including an integrated circuit and bond-pads electrically coupled to the integrated circuit, the method comprising:

constructing a plurality of electrically conductive through-substrate interconnects extending at least partially through the semiconductor substrate and in contact with corresponding bond-pads;

forming a metal layer at a back side of the semiconductor substrate; and

selectively coupling a back side portion of first interconnects of individual dies to the metal layer while keeping second interconnects of individual dies electrically isolated from the metal layer.

43. The method of claim 42 wherein selectively coupling a back side portion of first interconnects of individual dies to the metal layer comprises placing solder balls in contact with the back side portions of first interconnects and portions of the metal layer adjacent to the first interconnects.

44. The method of claim 42 wherein selectively coupling a back side portion of first interconnects of individual dies to the metal layer comprises coupling the back side portion of the first interconnects to the metal layer within the footprint of the respective dies.

45. The method of claim 42, further comprising:

depositing a dielectric layer onto the back side of the substrate and over the metal layer; and

forming first openings in the dielectric layer to expose the back side portions of the first interconnects and adjacent portions of the metal layer, and forming second openings in the dielectric layer to expose a back side portion of the individual second interconnects, wherein the metal layer is isolated from the second openings, and

selectively coupling a back side portion of first interconnects of individual dies to the metal layer while keeping second interconnects of individual dies electrically isolated from the metal layer comprises (a) placing solder balls in the first openings in direct contact with the corresponding first interconnects and adjacent portions of the metal layer, and (b) placing solder balls in the second openings in contact with the corresponding second interconnects and electrically isolated from the metal layer.

46. A method of fabricating a semiconductor substrate having integrated circuitry, a plurality of bond-pads electrically coupled to the integrated circuitry, and a plurality of electrically conductive through-substrate interconnects in contact with corresponding bond-pads, the method comprising:

forming an EMI shield at a back side of the semiconductor substrate that does not directly contact the interconnects; and

coupling an interconnect to the EMI shield with a solder ball in direct physical contact with a back side portion of the interconnect and a corresponding portion of the shield.