Low fabrication cost, fine pitch and high reliability solder bump

• US 20080054459A1
• Filed: 10/31/2007
• Published: 03/06/2008
• Est. Priority Date: 03/05/2001
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Application Number:
  US11/930,156
• Publication Number:
  US 20080054459A1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Claims

1. A chip comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a pad over said dielectric layer;

a passivation layer over said dielectric layer, an opening in said passivation layer exposing said pad, wherein said passivation layer comprises silicon nitride; and

a bump over said semiconductor substrate, wherein said bump is connected to said pad through said opening, and wherein said bump comprises a metal layer over said semiconductor substrate, wherein said metal layer is connected to said pad through said opening, a copper pillar over said metal layer, wherein said copper pillar has a height between 10 micrometers and 100 micrometers, and a nickel layer over said copper pillar, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a first transverse dimension smaller than a second transverse dimension of said nickel layer and smaller than a third transverse dimension of said metal layer, wherein said copper pillar has a first sidewall recessed from a second sidewall of said nickel layer and recessed from a third sidewall of said metal layer, wherein a distance between said first sidewall and said second sidewall is greater than 0.2 micrometers, wherein said metal layer has a top surface facing said copper pillar, wherein said top surface has a first region directly under said copper pillar and a second region not under said copper pillar, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar.

2. The chip of claim 1, wherein said semiconductor substrate comprises silicon.

3. The chip of claim 1, wherein said pad comprises aluminum.

4. The chip of claim 1, wherein said pad comprises copper.

5. The chip of claim 1, wherein said metal layer comprises titanium.

6. The chip of claim 1, wherein said metal layer comprises copper.

7. The chip of claim 1, wherein said metal layer has a thickness of between 500 and 2,000 angstroms.

8. The chip of claim 1, wherein said bump is further over said pad exposed by said opening.

9. The chip of claim 1, wherein said bump further comprises an electroplated metal on said nickel layer.

10. The chip of claim 1, wherein said bump further comprises a solder material on said nickel layer.

11. A chip comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a pad over said dielectric layer;

a passivation layer over said dielectric layer, an opening in said passivation layer exposing said pad, wherein said passivation layer comprises polymer; and

a bump over said semiconductor substrate, wherein said bump is connected to said pad through said opening, and wherein said bump comprises a metal layer over said semiconductor substrate, wherein said metal layer is connected to said pad through said opening, a copper pillar over said metal layer, wherein said copper pillar has a height between 10 micrometers and 100 micrometers, and a nickel layer over said copper pillar, wherein said nickel layer has a thickness between 1 and 10 micrometers, wherein said copper pillar has a first transverse dimension smaller than a second transverse dimension of said nickel layer and smaller than a third transverse dimension of said metal layer, wherein said copper pillar has a first sidewall recessed from a second sidewall of said nickel layer and recessed from a third sidewall of said metal layer, wherein a distance between said first sidewall and said second sidewall is greater than 0.2 micrometers, wherein said metal layer has a top surface facing said copper pillar, wherein said top surface has a first region directly under said copper pillar and a second region not under said copper pillar, and wherein said nickel layer comprises a first portion over said copper pillar and a second portion overhanging said copper pillar.

12. The chip of claim 11, wherein said semiconductor substrate comprises silicon.

13. The chip of claim 11, wherein said pad comprises aluminum.

14. The chip of claim 11, wherein said pad comprises copper.

15. The chip of claim 11, wherein said metal layer comprises titanium.

16. The chip of claim 11, wherein said metal layer comprises copper.

17. The chip of claim 11, wherein said passivation layer comprises polyimide.

18. The chip of claim 11, wherein said bump is further over said pad exposed by said opening.

19. The chip of claim 11, wherein said bump further comprises an electroplated metal on said nickel layer.

20. The chip of claim 11, wherein said bump further comprises a solder material on said nickel layer.