STRUCTURE OF WAFER LEVEL PACKAGE WITH AREA BUMP

• US 20080054460A1
• Filed: 11/05/2007
• Published: 03/06/2008
• Est. Priority Date: 12/13/2002
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Hung, Chih-Pin
• Granted Patent: US 7,576,436 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 : Bonding areas having different shapes
• CPC Class Codes: H01L 2224/0616 : Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A package structure with an area bump has at least a chip (also known as a die), a redistribution layer, a plurality of first bumps (normal bumps) and at least a second bump (area bump). The redistribution layer may reroute and integrate the bonding pads of the chip and incorporate the passive components therein.

Claims

1. A package structure, comprising:

at least a chip, comprising an active surface and a plurality of bonding pads on the active surface;

a passivation layer covering the active surface of the chip and exposing the bonding pads;

a redistribution layer on the passivation layer and over the bonding pads of the chip, wherein the redistribution layer comprises at least a dielectric layer and a patterned metal layer, wherein the patterned metal layer comprises a plurality of first bumping pads and at least a second bumping pad, and the patterned metal layer is electrically connected to the bonding pads;

a plurality of first bumps, respectively connected to the first bumping pads; and

at least a second bump, connected to the second bumping pad, wherein a size of the second bumping pad is larger than a size of one of the first bumping pads.

2. The structure of claim 1, wherein the redistribution layer further comprises at least one passive component.

3. The structure of claim 2, wherein the passive component is selected from the group consisting of a resistor, a capacitor and an inductor.

4. The structure of claim 1, wherein the first bumping pad is electrically connected to the bonding pads in a one-to-one fashion.

5. The structure of claim 1, wherein the second bumping pad is electrically connected to the bonding pads in a one-to-more fashion.

6. The structure of claim 5, wherein the size of the second bumping pad is about twice the size of one of the first bumping pads.

7. The structure of claim 5, wherein the bonding pads that are connected to the second bumping pad are of the same function.

8. The structure of claim 1, wherein a material of the dielectric layer is selected from the group consisting of epoxy resin, polyimide (PI) and benzocyclobutene (BCB).

9. The structure of claim 1, wherein the patterned metal layer is a stacked layer made of two or more metal layers.

10. The structure of claim 1, wherein the patterned metal layer is made of one or more selected from the group consisting of aluminum, titanium, copper, chromium and nickel.

11. The structure of claim 1, wherein the redistribution layer further comprises a middle metal layer and an inter-dielectric layer sandwiched between the dielectric layer and the patterned metal layer, and the middle metal layer disposed on the dielectric layer is connected to the bonding pads and to the first and second bumping pads through vias.

12. The structure of claim 1, further comprising a molding compound encapsulating the chip and the redistribution layer.

13. The structure of claim 1, further comprising a circuit pattern plate disposed between the redistribution layer and the bumps.

14. The structure of claim 1, further comprising a lead-frame disposed between the redistribution layer and the bumps.

15. The structure of claim 1, wherein the bumping pad further comprises at least one identification mark.

16. The structure of claim 15, wherein the shape of the identification mark differs from other bumping pads.

17. The structure of claim 1, wherein the first bumping pads are disposed around a periphery of the second bumping pad.

18. The structure of claim 1, wherein the second bumping pad electrically integrates plurality of power or ground pads.

19. The structure of claim 1, wherein the redistribution layer further comprises a high-k material.