TEST CHIP SOCKET

• US 20080054925A1
• Filed: 08/20/2007
• Published: 03/06/2008
• Est. Priority Date: 08/21/2006
• Status: Active Grant

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Ohkura, YOSHIHIRO
• Granted Patent: US 7,642,799 B2
• Time in Patent Office: Days
• US Class Current: 324/755
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67

Abstract

A test chip socket comprises a contact block fixed to a tester substrate, a tray mounted to the contact block, the tray having a convex part for positioning test target chips to a plurality of mount positions, and a plurality of probes each of which is held by the contact block and contacts the tester substrate and the test target chip, wherein each probe contacts with a terminal of each test target chip mounted to the mounting position when the tray mounting the plurality of the test target chip is fixed to the contact block.

Claims

1. A test chip socket, comprising:

a contact block fixed to a tester substrate;

a tray mounted to the contact block, the tray having a convex part for positioning test target chips to a plurality of mount positions; and

a plurality of probes each of which is held by the contact block and contacts the tester substrate and the test target chip, wherein each probe contacts with a terminal of each test target chip mounted to the mounting position when the tray mounting the plurality of the test target chip is fixed to the contact block.

2. The test chip socket according to claim 1, further comprising:

a positioning hole formed on the tray; and

a guide rod that is formed on the contact block and is inserted to the positioning hole.

3. The test chip socket according to claim 1, further comprising a cover that covers the test target chips mounted on the tray and fixes the tray to the contact block, and

wherein the tray comprises piercing holes to which the probes inserted, each piercing hole is formed in each of the plurality of mount positions,

the contact block comprises a base to which the probes are fixed, a table through which the probes pierce and on which the tray is placed, and a spring that support the table at a position separated from the base,

the cover connects to the base in a condition that the table is pushed into the base, and

each of the probes contacts with a terminal of the test target chip exposing from the piercing hole when the cover connects with the base.

4. A test system to which the test chip socket according to claim 1 is fixed, the test system comprising:

a tester substrate that tests signal processing circuits of magnetic sensor chips as the test target chips mounted to the contact block; and

a data obtaining device that obtains test result data representing test results of the test target chips mounted to each mount position via the tester substrate.

5. A test system to which the test chip socket according to claim 1 is fixed, the test system comprising:

a tester substrate;

a reader that reads identification data of the tray;

a data obtaining device that obtains test result data representing test results of the test target chips mounted to each mount position via the tester substrate; and

an output device that outputs the test result data by correlating with the identification data.

6. A method for testing a chip by using the test system according to claim 5, the method comprising the steps of:

mounting test target chips to the plurality of the mount positions;

reading the identification data from the tray;

obtaining test result data in a condition that the contact block fixes the tray to which the test target chips are mounted;

outputting the test result data by correlating the identification data;

removing the tray from the contact block;

selecting an acceptable chip from the plurality of the test target chips mounted to the tray in accordance with the test result data correlated with the identification data of the removed tray.

7. A test chip tray used as the tray for the test target chips according to claim 1, the test chip tray comprising:

convex parts that are higher than height of the test target chip, each convex part being formed in the mount position on one main surface of the test chip tray for positioning the test target chip; and

concave parts formed on another main surface, and wherein

each convex part can be set into each concave part so as to pile up the plurality of the test chip trays.